Backside Interconnect Frame Layout for Lower-Cost BEOL Integration
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Solution Overview
Problem
The complexity of manufacturing and integration in semiconductor devices leads to increased fabrication costs and time due to additional process steps, necessitating an improvement in the manufacturing process.
Innovation Solution
A semiconductor device design featuring a backside contact with an interconnect part that includes a lower and upper redistribution layer, an interconnect frame, and a passivation structure, which simplifies the back-end-of-line (BEOL) routing and allows for a modular design, along with a method for forming this structure that reduces fabrication costs and time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional manufacturing and integration methods are used for semiconductor devices, then device functionality and integration can be achieved, but fabrication cost and time increase due to complicated manufacturing steps and operations
Solution Approach 1:
The semiconductor device is divided into distinct modules: a first semiconductor device, a second semiconductor device, and an interconnect part. This segmentation allows each module to be manufactured and integrated independently, simplifying the overall manufacturing process and reducing fabrication time while maintaining device functionality.
Solution Approach 2:
The patent introduces a vertical stacking architecture where the first and second semiconductor devices are arranged in different vertical levels and connected through the interconnect part. This three-dimensional integration approach reduces the lateral footprint and simplifies interconnection routing, thereby reducing fabrication complexity and time.
2Ease of manufacture
If traditional manufacturing and integration methods are used for semiconductor devices, then device functionality and integration can be achieved, but fabrication cost increases due to additional process steps
Solution Approach 1:
The semiconductor device is divided into distinct modules: a first semiconductor device, a second semiconductor device, and an interconnect part. This segmentation allows each module to be manufactured and integrated independently, simplifying the overall manufacturing process and reducing fabrication time while maintaining device functionality.
Solution Approach 2:
The patent introduces a vertical stacking architecture where the first and second semiconductor devices are arranged in different vertical levels and connected through the interconnect part. This three-dimensional integration approach reduces the lateral footprint and simplifies interconnection routing, thereby reducing fabrication complexity and time.
Data Source
AI summary
The present disclosure provides a semiconductor device with an interconnect part and a method for forming the semiconductor device. The semiconductor device includes a first source/drain structure disposed over a carrier substrate, and a backside contact disposed over and electrically connected to the first source/drain structure. The semiconductor device also includes an interconnect part disposed over the backside contact. The interconnect part includes a lower redistribution layer electrically connected to the backside contact, and an upper redistribution layer disposed over the lower redistribution layer. The interconnect part also includes an interconnect frame disposed between and electrically connected to the lower redistribution layer and the upper redistribution layer. The interconnect part further includes a passivation structure surrounding the interconnect frame.