Backside Interconnect Layout for Lower-Capacitance IC Routing
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Solution Overview
Problem
The increasing complexity and density of integrated circuit (IC) devices lead to manufacturing defects and parasitic capacitance issues due to crowded interconnect structures, which hinder performance and reliability as devices shrink in size.
Innovation Solution
Implementing backside interconnects in integrated circuits, which reduces the complexity of topside interconnect structures, decreases parasitic capacitance, and enhances manufacturing flexibility by allowing side connections between contacts and interconnects, thereby reducing resistance and manufacturing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If interconnect structures are made denser to increase device capacity, then device density increases, but parasitic capacitance increases and manufacturing defects increase
Solution Approach 1:
The patent introduces backside interconnects that route signals through the third dimension (vertical direction through substrate thickness) rather than only in the planar direction. This dimensional transition allows interconnects to bypass crowded topside regions, reducing parasitic capacitance while maintaining high device density on the surface.
Solution Approach 2:
The interconnect structure is segmented into multiple independent layers: topside interconnects for local routing, backside interconnects for long-distance routing, and through-substrate vias for vertical connections. This segmentation distributes the routing function across different spatial zones, reducing congestion and parasitic effects in any single layer.
2Quantity of substance
If interconnect structures are made denser to increase device capacity, then device density increases, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is segmented into distinct stages: forming topside interconnects, creating backside interconnects, and establishing through-substrate connections. Each stage can be independently optimized and controlled, reducing overall process complexity despite the multi-layer structure.
Solution Approach 2:
By utilizing the vertical dimension for backside routing, the patent reduces the complexity burden on the planar interconnect layers. The three-dimensional routing architecture distributes complexity across multiple spatial dimensions rather than concentrating it in a single plane.
3Ease of manufacture
If traditional topside interconnects are used, then manufacturing is simpler, but parasitic capacitance increases and performance decreases
Solution Approach 1:
The patent maintains ease of manufacture for topside interconnects while introducing backside interconnects that operate in a separate vertical zone. This dimensional separation allows each interconnect type to be manufactured using optimized processes for its specific location, with through-substrate vias providing the bridge between layers.
Solution Approach 2:
Through-substrate vias act as intermediary connection elements that link the simple topside interconnect structure with the performance-enhancing backside interconnect structure. These vias enable the composite system to achieve both manufacturing simplicity and high performance by combining the advantages of both approaches.
Data Source
AI summary
A method of making an integrated includes steps of etching an opening in an insulating mask to expose a first dummy contact on a backside of the integrated circuit, depositing a conductive material into the opening, the conductive material contacting a sidewall of the first dummy contact, and recessing the conductive material to expose an end of the first dummy contact. The method also includes steps of depositing an insulating material over the conductive material in the opening, removing the first dummy contact from the insulating mask to form a first contact opening, and forming a first conductive contact in the first contact opening, the first conductive contact being electrically connected to the conductive material.