Backside Interconnect Layout With Mixed Line Widths for Power Delivery
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Solution Overview
Problem
As semiconductor chip designs shrink to accommodate increasing functionality and faster processing speeds, the resistivity and power consumption of transistors and interconnect wires increase, necessitating more efficient power delivery networks without compromising electrical performance.
Innovation Solution
The formation of two types of lines in a metal level using damascene processes, where a second type of line with a narrower width is inserted between adjacent first type lines, allowing for additional wiring and power delivery while reducing congestion in the front side metal layers by relocating power delivery networks to the backside of the semiconductor substrate using through-silicon vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional power rails are used in front side metal interconnect layers, then power delivery is achieved, but semiconductor wiring area is significantly consumed and limits available wiring for other purposes
Solution Approach 1:
The patent moves the power delivery network from the traditional front side metal interconnect layers to the backside of the semiconductor substrate. This dimensional relocation allows power rails to occupy backside wiring areas, thereby preserving front side wiring resources for signal routing, clock, and I/O functions while maintaining adequate power delivery capability through the substrate.
Solution Approach 2:
The patent segments the power delivery function from the signal routing function by creating separate power delivery networks on the backside of the substrate. This segmentation allows independent optimization of power delivery paths and signal routing paths, enabling more efficient use of wiring resources on the front side for high-speed signals and I/O operations.
2Productivity
If line widths are reduced to support increasing functionality, then more device circuits are accommodated, but resistivity and power consumption increase
Solution Approach 1:
The patent relocates power delivery to backside metal levels, creating dedicated power paths that are separate from the front side signal interconnects. This allows front side signal lines to be optimized for speed and density without being constrained by power delivery requirements, while backside power rails can be designed with appropriate widths to minimize resistivity and power loss.
3Speed
If operating frequencies are increased to improve processing speeds, then computing system functionality is enhanced, but power consumption increases
Solution Approach 1:
The patent separates power delivery functions to backside metal levels, allowing front side interconnects to be optimized for high-speed signal transmission without the constraints of integrated power delivery. The backside power network can provide stable power supply with minimized impedance, supporting higher operating frequencies while controlling power consumption through dedicated power paths.
Data Source
AI summary
A semiconductor structure with a first backside metal level that has a plurality of first type of lines and at least one second type line. The first type of lines have a wider top surface than the bottom surface and have a first width. The first type of lines each connect by a first via to a second backside metal level. Each of first type of lines and the second type line connect by a second via to a through-silicon via. The second type line is narrower than the first type of lines. Each of the second type line is between adjacent first type of lines. The second type line has a top surface that is in the middle of the first type of lines, below the first type of lines, above, or level with the top surface of the first type of lines.