Back-Side Interconnects for Non-Planar Semiconductor Diodes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of semiconductor diodes with non-planar transistor regions in integrated circuits (ICs) is challenging due to the lack of bulk semiconductor regions, leading to poor current carrying capabilities, especially for applications like ESD protection diodes, as existing efforts to employ non-planar bodies for diode fabrication have been unsuccessful in achieving sufficient current carrying capabilities.
Innovation Solution
The solution involves using non-planar semiconductor bodies with back-side interconnects to form p-n junction diodes, where the semiconductor bodies are doped on both sides and interconnected through doped-semiconductor and metallization on the back side, allowing for greater current carrying capability and concurrent front-side processing similar to transistors, enabling the integration of diodes with transistors in ICs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If planar doped wells are used within bulk semiconductor for diode fabrication, then current carrying capability is improved, but bulk semiconductor regions become less available as transistor density increases
Solution Approach 1:
The patent transitions from planar diode structures to vertical diode structures by utilizing the vertical dimension of non-planar semiconductor bodies. The p-n junction is formed vertically through the semiconductor body, with the anode and cathode contacts made on opposite sides of the vertical structure, thereby creating a three-dimensional diode architecture that does not consume additional bulk semiconductor area.
Solution Approach 2:
The non-planar semiconductor bodies are designed to serve dual purposes: functioning as transistor channels when viewed from the front side and as diode structures when viewed from the vertical perspective. This multi-functionality allows the same semiconductor structures to support both high-density transistor integration and diode fabrication without requiring separate bulk semiconductor regions.
2Adaptability or versatility
If non-planar semiconductor bodies are used for diode fabrication, then integration with non-planar transistors is improved, but current carrying capability becomes too low for applications like ESD protection diodes
Solution Approach 1:
The patent employs vertical diode structures formed within non-planar semiconductor bodies, utilizing the vertical dimension to create p-n junctions that extend through the semiconductor body. This vertical architecture increases the effective junction area and allows for higher current carrying capability while maintaining compatibility with non-planar transistor integration.
Solution Approach 2:
The patent uses composite structures combining non-planar semiconductor bodies with selectively doped regions. The semiconductor body maintains its non-planar geometry for transistor integration, while doped regions are formed within and around the non-planar structures to create functional diode regions with enhanced current carrying capability.
3Adaptability or versatility
If planar semiconductor diode regions are integrated with non-planar semiconductor transistor regions, then diode functionality is achieved, but integration difficulty increases
Solution Approach 1:
The patent designs non-planar semiconductor bodies that can function as either transistor channels or diode structures depending on the configuration of doped regions and contacts. This universality simplifies integration by allowing the same fabrication processes and structural approaches to be used for both transistor and diode formation, eliminating the need for separate planar diode regions.
Solution Approach 2:
Instead of forming planar diode regions within bulk semiconductor, the patent inverts the approach by forming vertical diode structures within non-planar semiconductor bodies. The p-n junction is created vertically through the semiconductor body rather than laterally within a planar region, fundamentally changing the geometric approach to diode formation.
Data Source
AI summary
Integrated circuit (IC) strata including one or more transistor and one or more semiconductor diode. A transistor may include one or more non-planar semiconductor bodies in which there is a channel region while the diode also includes one or more non-planar semiconductor bodies in which there is a p-type region, an n-type region, or both. One IC stratum may be only hundreds of nanometers in thickness and include both front-side and back-side interconnect levels. The front-side interconnect level is disposed over a front side of one or more of the non-planar semiconductor bodies and is coupled to at least one terminal of the transistor. The back-side interconnect level is disposed over a back side of one or more of the non-planar semiconductor bodies and is coupled to at least one terminal of the semiconductor diode.