Backside Interconnect Layout to Prevent FET Gate Oxide Plasma Damage
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Solution Overview
Problem
The challenge in semiconductor manufacturing is the risk of plasma-induced damage (PID) to field effect transistors (FETs) due to static electrical charges during the formation of backside interconnect structures, which can damage the thin gate oxide of FETs.
Innovation Solution
A semiconductor device design where the gate of the transistor is electrically connected to a seal ring structure through a diode, allowing process charges to be collected in the seal ring structure, referred to as the charge pool, thereby avoiding PID and protecting the gate of the transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If backside interconnect structures are formed using plasma processes, then interconnect functionality is achieved, but static electrical charges accumulate causing plasma-induced damage to FET gate oxide
Solution Approach 1:
A seal ring structure is introduced as an intermediary element between the plasma process environment and the FET gate oxide. This seal ring acts as a mediator that intercepts and collects static electrical charges generated during plasma deposition or etching of backside interconnect structures, preventing these charges from reaching and damaging the gate oxide. The seal ring is positioned in the gate extension region, creating a protective buffer zone that allows plasma processing to proceed while safeguarding sensitive transistor components.
2Productivity
If geometry size is scaled down to increase functional density, then production efficiency improves, but manufacturing complexity increases and susceptibility to plasma damage increases
Solution Approach 1:
The device structure is segmented into distinct functional regions with the seal ring structure forming a separate protective element in the gate extension region. This segmentation allows the plasma processing of backside interconnect structures to occur independently without directly exposing the FET gate oxide to harmful charges. The separated architecture enables continued scaling of functional density while the dedicated seal ring segment absorbs the increased manufacturing complexity of protecting scaled-down devices during plasma processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively mitigates the risk of plasma-induced damage by redirecting process charges away from the transistor gate, ensuring the integrity of the gate oxide and maintaining the resistance of the channel.
Implementation Method 1
allowing process charges to be collected in the seal ring structure, referred to as the charge pool
Implementation Method 2
a gate of the transistor is electrically connected to a seal ring structure through a diode
Data Source
AI summary
Provided are a semiconductor device and a method of forming the same. The semiconductor device includes a device layer having a frontside and a backside; a first interconnect structure disposed on the frontside of the device layer, and having a first seal ring structure; a second interconnect structure disposed on the backside of the device layer; and a diode and a transistor embedded in the device layer, wherein a gate of the transistor is electrically connected to the first seal ring structure by the diode.