Backside Interconnect Structures for Semiconductor Devices
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing device size and increasing integration density while minimizing defects, particularly in forming backside interconnect structures and power rails in semiconductor devices.
Innovation Solution
The method involves forming fine-pitch backside interconnect structures over a carrier substrate, bonding the substrate to these structures, and creating fins and power rails through the substrate, allowing for better overlay control and reduced device size, defects, and improved device density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional front-side interconnect structures are used, then device fabrication is straightforward, but device size reduction and integration density increase are limited
Solution Approach 1:
The patent moves interconnect structures from the traditional front-side (2D plane) to the backside of the substrate, utilizing the third dimension (depth/vertical space) to increase integration density without expanding the device footprint. This dimensional transition allows concurrent formation of power rails and signal lines in different spatial planes.
Solution Approach 2:
The interconnect system is segmented into separate functional layers: power rails formed in the backside substrate and signal interconnects formed in dielectric layers above the substrate. This segmentation allows independent optimization of power delivery and signal routing, reducing interference and enabling finer pitch dimensions.
2Length of moving object
If fine-pitch backside interconnect structures are formed, then device size and critical dimensions are reduced, but manufacturing precision and overlay control become more challenging
Solution Approach 1:
The backside interconnect structures and power rails are formed preliminarily before substrate bonding to the front-side device structures. This preliminary formation allows the use of relaxed pitch dimensions during fabrication, improving manufacturing precision and overlay control, while still achieving fine-pitch equivalent density after bonding.
3Use of energy by moving object
If power rails are extended through the substrate, then power delivery efficiency is improved, but device complexity and fabrication steps increase
Solution Approach 1:
The power rail formation process is merged with the backside interconnect structure fabrication. Both the power rails and signal interconnects are formed concurrently in the same dielectric layers and substrate regions, eliminating separate fabrication steps and reducing overall process complexity despite the extended functionality.
Data Source
AI summary
Backside interconnect structures having reduced critical dimensions for semiconductor devices and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure over a front-side of a substrate; a first backside interconnect structure over a backside of the substrate, the first backside interconnect structure including first conductive features having tapered sidewalls with widths that narrow in a direction away from the substrate; a power rail extending through the substrate, the power rail being electrically coupled to the first conductive features; and a first source/drain contact extending from the power rail to a first source/drain region of the first transistor structure.