Backside Interconnect Layout for Low-Resistance Signal Transmission
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Solution Overview
Problem
Existing semiconductor integrated circuits face challenges in optimizing metal track arrangements for long-distance signal transmission, leading to increased resistivity and reduced performance as signal paths are scaled down.
Innovation Solution
The use of backside metal lines with wider widths for signal transmission between logic circuits, in conjunction with frontside metal routing, reduces signal resistance and improves integrated circuit performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If metal track width is reduced for scaling down signal paths, then circuit integration density is improved, but signal resistivity increases
Solution Approach 1:
The patent utilizes the third dimension by forming wider metal tracks on the backside of the semiconductor substrate. This allows the signal transmission path to extend in the vertical dimension (through the substrate thickness) while maintaining wider effective conductive cross-section, thereby reducing resistivity without compromising frontside integration density.
Solution Approach 2:
The invention nests additional conductive structures within the substrate volume. By creating metal interconnects that traverse through and across the substrate, the effective conducting path is nested within the existing device structure, providing lower resistance pathways without occupying additional planar area.
2Adaptability or versatility
If metal track length is increased for long-distance signal transmission, then functional complexity is improved, but signal resistance increases
Solution Approach 1:
The patent segments the signal transmission path into multiple sections: frontside metal interconnects, through-substrate vias, and backside metal interconnects. Each segment is optimized independently, with the backside providing wide-track low-resistance pathways for long-distance transmission while the frontside maintains high-density integration.
Solution Approach 2:
The substrate itself acts as an intermediary structure that carries signal transmission pathways. By routing signals through the substrate thickness via wider backside metal tracks, the invention provides a low-resistance mediator for long-distance signal transmission between frontside logic circuits.
3Reliability
If metal track width is increased to reduce resistance, then signal transmission quality is improved, but area occupied by metal tracks increases
Solution Approach 1:
The invention resolves this contradiction by moving the wide-track metal interconnects to the backside of the substrate, utilizing the vertical dimension. This allows wide tracks for low resistance to exist without consuming precious frontside planar area, as the backside is typically less constrained for routing purposes.
Data Source
AI summary
An integrated circuit includes a driver cell and at least one transmission cell. The driver cell includes a first active area and a second active area, and a first conductive line coupled to the first active area and the second active area on a back side of the integrated circuit. The at least one transmission cell having a second cell height includes a third active area and a fourth active area, a second conductive line coupled to the third active area and the fourth active area on the back side of the integrated circuit, and a conductor coupled to the third active area and the fourth active area. The integrated circuit further includes a third conductive line coupled between the first conductive line and the second conductive line on the back side to transmit a signal between the driver cell and the at least one transmission cell.