Back Side Metal Interconnects for Semiconductor-on-Insulator Circuits
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Solution Overview
Problem
In integrated circuits, traditional metal interconnect layouts result in increased area and parasitic capacitance due to the need for multiple layers and close proximity of metal lines, which affects performance and cost, especially in high-speed and high-frequency circuits.
Innovation Solution
A transferred silicon-on-insulator structure with a back side metal interconnect layer is formed by etching holes through the insulating layer to connect active circuit elements, reducing parasitic capacitance and providing layout flexibility, while also aiding in heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional front-side metal interconnect layers are used to connect circuit elements, then electrical connectivity is achieved, but parasitic capacitance increases and layout area expands
Solution Approach 1:
The patent moves the metal interconnect layer from the front side to the back side of the semiconductor structure, utilizing the z-dimension (vertical dimension) to relocate interconnects. This dimensional transition allows interconnects to be positioned on the opposite face of the insulating layer, reducing parasitic capacitance by increasing separation from front-side structures while maintaining electrical connectivity through the insulator via formed openings.
Solution Approach 2:
The patent inverts the conventional interconnect architecture by placing metal interconnects on the back side of the semiconductor structure rather than the front side. This inversion reverses the traditional layering sequence, with the metal interconnect layer positioned after the insulating layer and semiconductor layer, thereby reducing parasitic capacitance effects that plague conventional front-side interconnect designs.
2Reliability
If multiple metal layers and contacts are used to connect upper and lower level interconnects, then electrical connectivity is achieved, but device complexity and manufacturing steps increase
Solution Approach 1:
The patent extracts the metal interconnect layer from the conventional front-side position and relocates it to the back side of the semiconductor structure. This extraction simplifies the overall device architecture by eliminating the need for multiple intermediate metal layers and contacts that would otherwise be required to achieve connectivity between upper and lower level interconnects on the same face.
Solution Approach 2:
The back-side metal interconnect layer serves multiple functions simultaneously: it provides electrical connectivity between circuit elements, acts as a ground or power plane, and serves as a heat dissipation path. This multi-functionality reduces the need for separate dedicated layers for each function, thereby reducing overall device complexity.
3Area of stationary object
If metal interconnect lines are placed in close proximity to reduce area, then layout area is reduced, but parasitic capacitance between lines increases
Solution Approach 1:
By relocating the metal interconnect layer to the back side of the semiconductor structure, the patent utilizes the vertical dimension to increase separation between interconnect lines and front-side structures. This dimensional relocation allows for reduced layout area while maintaining low parasitic capacitance, as the back-side positioning inherently increases vertical separation from front-side circuit elements.
4Ease of manufacture
If traditional interconnect structures are used, then manufacturing process is straightforward, but heat dissipation efficiency is reduced
Solution Approach 1:
The patent extracts the metal interconnect layer from the front side and positions it on the back side of the semiconductor structure, where it can serve as an effective heat sink. This extraction allows the interconnect layer to directly contact the back side of the semiconductor substrate, creating an efficient thermal pathway that improves heat dissipation without significantly complicating the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic capacitance and area requirements, enhancing performance and cost-effectiveness for high-speed circuits by using back side interconnects, which are more efficient and thermally advantageous compared to traditional front-side interconnects.
Implementation Method 1
a metal interconnect layer is formed on the second surface of the insulator layer and inside the hole in the insulator layer. The metal interconnect layer electrically couples a plurality of the active or reactive circuit elements to each other
Implementation Method 2
aiding in heat dissipation
Data Source
Figure 1~2
Figure 3
Figure 4A~4C
AI summary
An integrated circuit fabricated on a semiconductor-on-insulator transferred layer is described. The integrated circuit includes an interconnect layer fabricated on the back side of the insulator. This interconnect layer connects active devices to each other through holes etched in the insulator. This structure provides extra layout flexibility and lower capacitance, thus enabling higher speed and lower cost integrated circuits.