Backside Interconnect Patterning for Tight-Registration Transistor Layers
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Solution Overview
Problem
Legacy techniques face challenges in achieving tight-pitch interconnects on both sides of transistor layers due to wafer distortion during processing, leading to registration issues and scalability problems as the number of transistors increases.
Innovation Solution
The technique involves patterning back side metal contact and interconnect layers before forming the transistor layer, using a sacrificial material like titanium nitride, which is later replaced with conductive metals like copper or tungsten, allowing for tight registration and minimal distortion impact on the resulting connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If back side metal interconnects are patterned after transistor layer formation, then processing sequence is simplified, but wafer distortion causes registration issues and loose alignment
Solution Approach 1:
The back side metal interconnect pattern is formed in advance on the carrier substrate before the transistor layer is transferred. This preliminary patterning allows the interconnect structure to be established while the carrier substrate maintains dimensional stability, avoiding registration issues that would occur if patterning were performed after transistor layer formation when wafer distortion is present
2Productivity
If transistor layer density increases, then chip functionality improves, but interconnect registration accuracy deteriorates due to wafer distortion
Solution Approach 1:
The back side metal interconnect pattern is created before transistor layer transfer, enabling high-density transistor placement without compromising interconnect alignment accuracy
Solution Approach 2:
The interconnect pattern is copied onto the carrier substrate in advance, creating a stable template that remains unchanged during subsequent transistor layer processing and transfer operations
3Reliability
If tight-pitch interconnects are achieved, then signal quality improves, but processing complexity increases due to distortion management
Solution Approach 1:
The back side metal interconnect pattern is formed in advance on the carrier substrate before transistor layer transfer, enabling tight-pitch interconnects to be achieved without the added complexity of managing wafer distortion during patterning operations
Data Source
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Figure 2A~2B
AI summary
Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for forming a package that has a transistor layer with a front side metal interconnect layer and a back side metal contact and interconnect layer. In particular, back side metal contact and interconnect layers may be patterned before a transistor layer, or other device layer, is formed on the patterned layers and before front side metal interconnect layers are formed on the transistor layer. Other embodiments may be described and/or claimed.