Backside Interconnect Layout for Vertical Nanosheet Transistors
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Solution Overview
Problem
The semiconductor industry faces challenges in fabricating three-dimensional designs, such as vertical transistors, due to issues in device density, performance, and cost, particularly in achieving efficient interconnections and reducing capacitance in nanometer technology process nodes.
Innovation Solution
A semiconductor arrangement featuring a vertical unit cell architecture with nanosheets and backside interconnections, allowing for flexible interconnection of transistors and reducing capacitance through the use of vertical nanowire devices, which can include three-dimensional finFETs, gate-all-around transistors, or planar MOSFETs, with specific processes like shallow trench isolation and replacement gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional designs such as vertical transistors are implemented to increase device density, then device density is improved, but fabrication complexity increases
Solution Approach 1:
The fabrication process is divided into distinct stages: forming semiconductor fins, depositing gate electrodes, creating source/drain regions, and implementing backside interconnections. Each stage is independently optimized, allowing complex 3D structures to be built through manageable sequential steps rather than attempting to create the entire structure in one process
Solution Approach 2:
The patent introduces backside interconnections that access transistor components from the substrate backside rather than only from the top surface. This adds a vertical dimension to the interconnection architecture, enabling shorter contact lengths and reduced capacitance while maintaining the high device density achieved through vertical transistor structures
2Ease of manufacture
If conventional interconnection methods are used in nanometer technology, then manufacturing simplicity is maintained, but capacitance increases
Solution Approach 1:
Instead of routing interconnections only through the top surface of the substrate, the patent inverts the approach by creating backside interconnections that access transistor components from the opposite side. This inversion allows interconnection paths to bypass bulky top-surface routing structures, significantly reducing parasitic capacitance while still using standard semiconductor fabrication techniques
Data Source
AI summary
A method of forming a semiconductor arrangement includes forming a first source pad over a semiconductor layer. A first nanosheet is formed contacting the first source pad. A gate pad is formed adjacent the first nanosheet. A first drain pad is formed over the gate pad and contacting the first nanosheet. A backside interconnect line is formed under the gate pad and the first source pad. A first backside contact is formed contacting at least one of the backside interconnect line, the first source pad, or the gate pad.