Backside Interconnection Layout for Semiconductor Heat Dissipation
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Solution Overview
Problem
Existing semiconductor devices face challenges in efficiently dissipating heat generated by transistors and maintaining reliability due to the routing complexity at the back-end-of-line (BEOL) of FinFETs and nanosheet transistors, particularly with the formation of metal patterns on the backside.
Innovation Solution
The semiconductor device incorporates a second interconnection layer on the backside of the integrated circuit layer with a dummy metal structure acting as a heat sink, spaced apart from the interconnection structures, and an insulating pattern with high thermal conductivity to enhance heat dissipation, while maintaining electrical insulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If metal patterns are formed on the backside of the integrated circuit layer for power delivery, then power delivery capability is improved, but heat dissipation efficiency deteriorates due to routing complexity
Solution Approach 1:
The backside interconnection layer is segmented into functionally distinct regions: active interconnection structures for power delivery, dummy metal structures for heat dissipation, and insulating patterns for plasma protection. This segmentation allows each region to optimize its specific function without interfering with others, resolving the contradiction between power delivery and heat dissipation.
Solution Approach 2:
Different regions of the backside interconnection layer are assigned different local qualities: conductive metal patterns in power delivery zones, high thermal conductivity dummy metal structures in heat dissipation zones, and insulating materials in plasma protection zones. This local differentiation enables simultaneous optimization of power delivery, heat dissipation, and manufacturing reliability.
2Ease of manufacture
If the backside thinning process is performed to address routing complexity, then manufacturing feasibility is improved, but heat dissipation capability deteriorates
Solution Approach 1:
The patent transitions from planar heat dissipation to three-dimensional heat management by forming dummy metal structures with specific thicknesses and spatial arrangements on the backside. This dimensional approach allows heat to be dissipated through vertical and lateral pathways simultaneously, maintaining heat dissipation capability despite backside thinning for manufacturing feasibility.
3Reliability
If insulating patterns are added to protect from plasma damage, then reliability is improved, but device complexity increases
Solution Approach 1:
The insulating patterns are merged with the existing interconnection layer structure during the same manufacturing process steps. The insulating material is deposited and patterned together with the metal layers, combining multiple functions (power delivery, heat dissipation, and plasma protection) into a single integrated structure, thereby improving reliability without proportionally increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves heat dissipation and reduces damage from plasma during manufacturing, enhancing the overall reliability and performance of the semiconductor device.
Implementation Method 1
a dummy metal structure spaced apart from the interconnection structure in a first direction, and wherein the dummy metal structure does not overlap the connection terminal in a second direction that is perpendicular to the first direction
Implementation Method 2
incorporates a second interconnection layer on the backside of the integrated circuit layer with a dummy metal structure acting as a heat sink
Implementation Method 3
an insulating pattern with high thermal conductivity to enhance heat dissipation, while maintaining electrical insulation
Implementation Method 4
an insulating pattern with high thermal conductivity to enhance heat dissipation, while maintaining electrical insulation
Data Source
AI summary
A semiconductor device includes: an integrated circuit layer including a transistor; a first interconnection layer on a front side of the integrated circuit layer; a second interconnection layer on a back side of the integrated circuit layer; and a connection terminal on the second interconnection layer, wherein the second interconnection layer includes: an insulating layer; an interconnection structure in the insulating layer; an active contact disposed between the interconnection structure and a source/drain region of the transistor and connected to the source/drain region; and a dummy metal structure spaced apart from the interconnection structure in a first direction, and wherein the dummy metal structure does not overlap the connection terminal in a second direction that is perpendicular to the first direction.