Backside Interposer Power Routing for Thin Semiconductor Dies
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Solution Overview
Problem
The shrinkage of advanced semiconductor technologies is limited by the input/output (I/O) of signals and power functionality due to the footprint of elements such as vias, necessitating an improved concept for providing power to silicon dies.
Innovation Solution
The integration of an interposer directly attached to the backside of the semiconductor substrate, which allows for horizontal and vertical power delivery, reduces substrate thickness, and incorporates electrical elements, enhancing power supply, cooling, and positioning freedom.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If metallization and routing density is increased to provide more signals and power to the silicon die, then the I/O capability and power functionality are improved, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent introduces an interposer layer that adds a new dimensional level to the interconnect architecture. Instead of increasing routing density within the silicon die plane, power and signals are delivered through a third dimension via the interposer, which contains through-silicon vias (TSVs) that penetrate vertically through the substrate. This dimensional transition resolves the contradiction by providing additional power and signal pathways without increasing in-plane routing complexity.
Solution Approach 2:
The interposer acts as an intermediary structure between the silicon die and the external package. It mediates the power and signal delivery by receiving inputs from external traces and distributing them through TSVs to the die's front side, thereby enhancing power functionality without directly increasing the complexity of the die's internal routing.
2Length of moving object
If substrate thickness is reduced to enable thinner semiconductor devices, then the device profile and integration density are improved, but the mechanical strength and thermal management capability deteriorate
Solution Approach 1:
The patent employs a composite structure consisting of multiple materials with different properties: the interposer substrate (e.g., silicon, glass, or ceramic), the conductive TSV materials (copper, aluminum), and the dielectric materials filling the vias. This composite approach allows the thin substrate to maintain mechanical strength through the inherent strength of individual layers while enabling thermal management through materials with high thermal conductivity, such as diamond or copper-filled vias.
Solution Approach 2:
The structure implements a nested configuration where TSVs are embedded within the interposer substrate, and the substrate itself is part of a larger package structure. This nesting allows the thin substrate to be supported by the surrounding structural elements, maintaining mechanical integrity despite reduced thickness.
3Power
If more power is delivered to the silicon die through increased routing density, then the power functionality is improved, but the heat generation and thermal management difficulty increase
Solution Approach 1:
The patent replaces traditional planar thermal management approaches with a three-dimensional thermal conduction system. Heat generated at the die is conducted vertically through the TSVs and interposer substrate via direct thermal conduction, bypassing the need for complex in-plane heat spreading mechanisms. This substitution of thermal management approach enables efficient heat removal alongside enhanced power delivery.
Solution Approach 2:
The interposer structure utilizes composite materials with high thermal conductivity, such as diamond layers or copper-filled vias, to create efficient thermal pathways. These materials conduct heat away from the die effectively, managing the thermal load generated by increased power delivery without requiring additional thermal management complexity.
4Power
If traditional power delivery methods are used with increased routing density, then power functionality is improved, but the manufacturing cost and process complexity increase
Solution Approach 1:
The interposer and TSV structure are fabricated in advance as a separate component before final assembly with the silicon die. This preliminary fabrication allows standard, well-established semiconductor manufacturing processes to be used for creating the power delivery infrastructure, reducing the need for complex, costly modifications to the die fabrication process itself and enabling more economical mass production.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device comprises a semiconductor die comprising a semiconductor substrate and a plurality of transistors arranged at a front side of the semiconductor substrate. Further, the semiconductor die comprises a first electrically conductive structure extending from the front side of the semiconductor substrate to a backside of the semiconductor substrate and a second electrically conductive structure extending from the front side of the semiconductor substrate to the backside of the semiconductor substrate. The semiconductor device further comprises an interposer directly attached to the backside of the semiconductor substrate. The interposer comprises a first trace electrically connected to the first electrically conductive structure of the semiconductor die. Further the interposer comprises the first trace or a second trace electrically connected to the second electrically conductive structure of the semiconductor die.