Backside I/O TSV Routing With Floating Wells for Low Capacitance
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Solution Overview
Problem
The high parasitic capacitance in back side I/O interconnects of semiconductor components, due to thin dielectric liners and large device sizes, negatively impacts signal transceiving, and existing ESD protection devices exacerbate this issue.
Innovation Solution
Implementing I/O TSV connections and rails in a floating well of opposite conductivity type, separated by a reverse-biased junction, which reduces parasitic capacitance and integrates an ESD protection circuit to mitigate these effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thin dielectric liner is used to isolate the TSV conductor from the substrate, then electrical isolation is achieved, but parasitic capacitance increases significantly
Solution Approach 1:
A floating well of opposite conductivity type is introduced as an intermediary structure between the TSV conductor and the substrate. This floating well acts as a mediator that reduces the parasitic capacitance while maintaining electrical isolation, effectively resolving the contradiction between achieving isolation and minimizing harmful capacitance effects.
Solution Approach 2:
The conductivity type parameter of the semiconductor region surrounding the TSV is changed by forming a floating well of opposite conductivity type. This parameter change fundamentally alters the electrical characteristics at the TSV-substrate interface, reducing parasitic capacitance while preserving isolation functionality.
2Reliability
If ESD protection devices are added to protect I/O terminals, then device reliability improves, but parasitic capacitance increases due to large device sizes
Solution Approach 1:
The ESD protection circuit is nested within the existing well structure of the semiconductor device. By integrating the ESD protection functionality into the floating well architecture, the solution provides protection without requiring separate large-area devices that would increase parasitic capacitance.
Solution Approach 2:
The floating well structure serves multiple functions simultaneously: it provides electrical isolation, reduces parasitic capacitance, and enables ESD protection. This multi-functionality eliminates the need for separate dedicated ESD protection devices that would consume additional area and increase capacitance.
3Productivity
If device density is increased in the front end, then productivity improves, but the strain on interconnects to power supply terminals increases
Solution Approach 1:
The power delivery network is moved from the traditional planar interconnect layer to the vertical dimension by implementing it on the back side of the substrate. This dimensional change allows high-density front-end devices to be connected to power supplies through TSVs without creating complex planar interconnect routing challenges.
Solution Approach 2:
The power delivery function is segmented from the signal routing function by placing power supply terminals and the PDN on the back side while keeping active devices on the front side. This segmentation simplifies the interconnect architecture by separating power distribution from signal routing paths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Significantly reduces parasitic capacitance and protects I/O terminals from electrostatic discharges, enhancing signal transceiving efficiency and device reliability.
Implementation Method 1
a reverse-biased junction, which reduces parasitic capacitance
Implementation Method 2
the low thickness of this liner and its relatively large surface area are responsible for the creation of an important parasitic capacitance between the nanoTSV conductor and the surrounding substrate
Implementation Method 3
the nanoTSVs that transmit I/O signals are required to be electrically isolated from that material. This is realized by providing a dielectric liner around the electrically conductive centre of the TSV.
Data Source
Figure 1C~1b
Figure 2a~3b
Figure 4a~5
AI summary
The invention is related to a semiconductor component, for example an integrated circuit chip, comprising a semiconductor substrate (1) having active devices (7) at the front side thereof and I/O terminals (19) at the back side of the component. The terminals are connected to the active devices through TSV connections (16b) and buried rails (15b) in an area (5) of the substrate that is separate from the area (4) in which the active devices are located. According to the invention, the I/O TSV connections (16b) are located in a floating well (25) of the substrate that is separated from the rest of the substrate by a second well (26) formed of material of the opposite conductivity type compared to the material of the floating well. The second well (26) comprises at least one contact (28) configured to be coupled to a voltage that is suitable for reverse-biasing the junction (27) between the floating well (25) and the second well (26). In this way, a small capacitance is placed in series with the large parasitic capacitance generated by a thin dielectric liner that isolates the I/O TSVs and I/O rails from the substrate, thereby mitigating the negative effect of the large parasitic capacitance. According to preferred embodiments, additional contacts and conductors are provided which are configured to create an ESD protection circuit for protecting the I/O TSVs (16b) and the I/O rails (15b) from electrostatic discharges.