Backside Isolation Etch for Uniform Front-End Transistor Structures
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Solution Overview
Problem
As transistors are scaled down, yield, performance, and reliability issues arise due to tapered etching and non-uniform contours, particularly in deep etches between dimensionally constrained features, leading to excessive erosion and tapering of device features, which impact device reliability and introduce process variation.
Innovation Solution
Improved isolation structures are formed from the wafer back-side, using a back-end-of-line (BEOL) etch to separate transistors, allowing for a narrower etch front on the front-side and minimizing process variation by reducing subsequent operations, enabling the use of low-permittivity and etch-resistant dielectrics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If front-side etching is performed to create deep isolation structures, then isolation depth is improved, but etch tapering causes excessive widening of the front-side opening and erosion of adjacent metallization
Solution Approach 1:
The patent performs the isolation etch from the backside of the substrate instead of the frontside. This inversion allows the etch front to be located at the backside surface where it does not interfere with frontside metallization structures, eliminating the tapering and erosion problems that occur when etching from the frontside.
Solution Approach 2:
The patent changes the etching direction from the frontside to the backside, utilizing the third dimension (substrate thickness) to resolve the conflict between achieving sufficient isolation depth and maintaining frontside feature uniformity. By etching from the opposite side, the process avoids direct interaction with the constrained frontside features.
2Reliability
If front-side etching is performed with constrained features, then isolation is achieved, but metallization erosion and rounding occur due to tapering
Solution Approach 1:
By inverting the etch direction to start from the backside, the etch front is positioned away from the metallization structures on the frontside. This eliminates the harmful erosion and rounding effects that occur when the etch front interacts with adjacent metallization during frontside etching.
Solution Approach 2:
The backside surface acts as an intermediary location for the etch front, allowing the etching process to proceed without directly interacting with the sensitive frontside metallization structures. This intermediary positioning prevents the harmful effects of erosion while still achieving the required isolation.
3Ease of manufacture
If front-side processing is performed early in the process flow, then isolation structures can be formed, but subsequent processing constraints limit material choices and increase process variation
Solution Approach 1:
The patent performs the isolation etch as a back-end-of-line (BEOL) process after the frontside structures are already formed. This preliminary formation of frontside structures allows subsequent backside processing to use a wider range of materials and processes without constraining earlier steps, thereby increasing material selection flexibility.
Solution Approach 2:
By inverting the process sequence to perform isolation etching after frontside processing rather than before, the patent eliminates the constraints that early frontside etching imposes on material choices. The backside etch can use materials and processes optimized for the specific isolation requirements without affecting frontside structure formation.
Data Source
AI summary
Isolation structures between transistors in integrated circuit (IC) devices. An IC device includes transistors coupled to an interconnect network, and between the transistors a dielectric structure with a wider width away from the interconnect network and a narrower width nearer the interconnect network. Dielectric structures with wider back-side widths may separate gate electrodes and/or source and drain contacts of the transistors. The dielectric structures may be formed by etching an opening between metallization structures of the transistors from a back side of the device substrate and by depositing liner and fill dielectrics over the back-side opening.