Backside Isolation Module Layout for GAA FET Power Contacts
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Solution Overview
Problem
Backside power delivery in semiconductor chips poses challenges in patterning electrical contact features isolated from one another by isolation modules within tight spaces without impacting transistor performance on the front side.
Innovation Solution
A method for forming a gate-all-around field-effect transistor (GAA FET) involving placeholder formation, removal, cavity shaping, contact layer creation, silicide formation, and dielectric liner deposition to isolate metal contacts with inter-layer dielectric (ILD) on the backside, while protecting source/drain epitaxial layers on the front side.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If backside power delivery is implemented to eliminate front side interconnect sharing, then power delivery efficiency is improved and manufacturing cost is reduced, but patterning electrical contact features in tight spaces becomes more difficult without impacting front side transistor performance
Solution Approach 1:
The method performs placeholder formation and removal, cavity shaping, and isolation module formation on the backside of the substrate before completing frontside transistor fabrication. This preliminary action on the backside enables subsequent frontside processing to proceed without interference, resolving the contradiction by separating the timing of backside power delivery structure formation from frontside transistor fabrication.
Solution Approach 2:
The patent divides the substrate processing into distinct frontside and backside operations, with isolation modules formed on the backside to separate electrical contact features. This segmentation allows independent optimization of backside power delivery patterning without compromising frontside transistor performance, addressing both power delivery efficiency and patterning difficulty.
2Reliability
If isolation modules are formed to separate electrical contact features on the backside, then electrical isolation is improved, but parasitic resistance increases due to tight spacing constraints
Solution Approach 1:
The isolation modules are formed with specific local properties on the backside of the substrate, using materials and dimensions optimized for electrical isolation while minimizing parasitic resistance. The isolation module geometry and material composition are tailored to provide adequate isolation between electrical contact features within tight spacing constraints, resolving the contradiction between electrical isolation and parasitic resistance.
3Manufacturing precision
If multiple processing steps are performed on the backside before frontside completion, then backside power delivery structure quality is improved, but process complexity increases
Solution Approach 1:
The patent performs placeholder formation, placeholder removal, cavity shaping, contact layer formation, silicide formation, and isolation module formation on the backside before frontside transistor fabrication is completed. This preliminary action sequence enables high-quality backside power delivery structures to be formed with controlled processing steps, improving manufacturing precision while managing process complexity through systematic sequencing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient isolation of metal contacts on the backside of semiconductor chips, minimizing parasitic resistance and optimizing metal layer fabrication, thus enhancing chip performance and reducing costs.
Implementation Method 1
performing a placeholder removal process to remove the placeholders selectively to the substrate and the STIs
Implementation Method 2
performing a substrate removal process to selectively etch the substrate against the RMG stacks and form ILD recesses between adjacent metal contacts
Implementation Method 3
performing a silicide formation process to form an interface on the contact layer
Data Source
AI summary
A method of forming a portion of a gate-all-around field-effect transistor (GAA FET) includes forming placeholders, each interfacing with an extension region electrically isolated from replacement-metal-gate (RMG) stacks by inner spacers, in recesses formed within portions of a substrate isolated by shallow trench isolations (STIs), the recesses extending into a front inter-layer dielectric (ILD) formed on the substrate, removing the placeholders selectively to the substrate and the STIs, forming a cavity at an exposed surface of the extension region within each of the recesses, forming a contact layer within the cavity, forming an interface on the contact layer, and a contact metallization process to form a metal contact within each of the recesses, selectively etching the substrate against the RMG stacks and form ILD recesses between adjacent metal contacts, forming a dielectric liner surrounding the metal contacts, and forming a back ILD in each of the ILD recesses.