Backside Isolation Structure for MOL Contact Tip-to-Tip Scaling
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Solution Overview
Problem
As integrated circuits (ICs) scale downward in size, device middle-of-line (MOL) contact tip-to-tip patterning becomes increasingly challenging, particularly due to the need for improved backside contact cut patterning techniques that enable better MOL tip-to-tip scaling.
Innovation Solution
The semiconductor structure incorporates a backside isolation region with a reverse tapered profile, which is embedded within the metal contact region and extends into the interlevel dielectric layer, electrically isolating adjacent source/drain regions and allowing for precise tip-to-tip spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional frontside contact patterning is used, then manufacturing process is simpler, but MOL tip-to-tip scaling precision deteriorates
Solution Approach 1:
The patent performs contact isolation patterning from the backside of the wafer instead of the conventional frontside approach. The backside isolation region is formed by etching through the backside surface to the metal contact region, which enables precise tip-to-tip spacing control while simplifying the overall process by avoiding complex frontside patterning steps at critical dimensions.
Solution Approach 2:
The invention transitions the contact isolation patterning operation from the frontside (2D planar patterning) to the backside (3D vertical etching). This dimensional change allows the isolation region to be formed with precise depth control through the metal contact layer, achieving better tip-to-tip scaling precision without the limitations of conventional planar patterning.
2Manufacturing precision
If backside isolation region with reverse tapered profile is formed, then electrical isolation precision is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent employs a reverse tapered profile for the backside isolation region, where the etched feature is narrower at the top (metal contact region interface) and wider at the bottom (backside surface). This parameter change in the geometric profile enables precise electrical isolation at the critical metal contact interface while maintaining manufacturability through controlled etch parameters.
3Quantity of substance
If IC size is scaled downward to increase device density, then device density is improved, but contact tip-to-tip patterning difficulty increases
Solution Approach 1:
By inverting the patterning approach to work from the backside, the method achieves precise tip-to-tip spacing control even as device dimensions scale down. The backside etching approach provides better control over the isolation region geometry at reduced dimensions, overcoming the patterning difficulties associated with high-density scaling.
Data Source
AI summary
A semiconductor structure includes a front-end-of-line level formed by a plurality of field effect transistors. Each field effect transistor includes a source/drain region disposed on opposite sides of the field effect transistor. A metal contact region is disposed above and in contact with a first surface of two adjacent source/drain regions. Each of the two adjacent source/drain regions correspond to a field effect transistor. A backside isolation region cuts through the metal contact region from a backside of the plurality of field effect transistors for electrically isolating the two adjacent source/drain regions.