Backside-Filled Isolation Regions for Balanced NMOS and PMOS Strain
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Solution Overview
Problem
Existing three-dimensional transistor architectures face challenges in achieving simultaneous performance improvement for both PMOS and NMOS transistors due to the use of a single isolation material, which can either enhance one type of transistor at the expense of the other, and the complexity of deposition and etching processes from the front side of the device layer is cumbersome.
Innovation Solution
The isolation materials in the transistor assembly are selectively deposited from the back side of the device layer, allowing for different strain materials to be used in NMOS and PMOS regions by masking, etching, and filling cavities with a second isolation material, such as air gaps, to improve performance of both transistor types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single isolation material is used for both PMOS and NMOS transistors, then the fabrication process is simplified, but the performance of one transistor type is improved at the expense of the other
Solution Approach 1:
The isolation regions are segmented into first isolation regions adjacent to PMOS transistors and second isolation regions adjacent to NMOS transistors. Different isolation materials can be applied to each segment, allowing optimized strain engineering for each transistor type while maintaining separate control over their respective isolation characteristics.
Solution Approach 2:
Different isolation materials with specific strain properties are applied locally to different regions: a first isolation material is applied to first isolation regions adjacent to PMOS transistors, and a second isolation material is applied to second isolation regions adjacent to NMOS transistors. This local differentiation enables each transistor type to benefit from isolation materials optimized for its specific performance requirements.
2Reliability
If different isolation materials are used for PMOS and NMOS regions, then transistor performance is optimized, but the deposition and etching processes become more complex
Solution Approach 1:
The approach transitions from front-side processing to back-side processing for isolation material deposition. By accessing the isolation regions from the back side of the device layer, the process avoids the complexity of front-side deposition and etching operations, simplifying the overall fabrication sequence while enabling different isolation materials to be applied to different transistor regions.
3Ease of manufacture
If front side deposition and etching processes are used, then isolation materials can be applied, but the process becomes cumbersome and damages other structures
Solution Approach 1:
Instead of applying isolation materials from the front side of the device layer, the process inverts the approach by depositing and etching isolation materials from the back side. This inversion allows isolation region modification without interfering with front-side transistor structures, eliminating damage to other components while maintaining ease of manufacture.
Data Source
Figure 1A~1B
Figure 2
Figure 3A~3B
AI summary
An integrated circuit (IC) device includes a first semiconductor region, a second semiconductor region, and a contact coupled to the first semiconductor region. The contact extends away from the semiconductor region in a direction. The IC device also includes an isolation region adjacent to the first semiconductor region and adjacent to the second semiconductor region. The isolation region includes a first isolation subregion and a second isolation subregion. A boundary between the first and second isolation subregions is substantially curved towards the direction.