Backside Lead IC Package for Clock Tree and PDN Thermal Relief
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Solution Overview
Problem
Integrated circuit (IC) packages face thermal constraints and inefficiencies in power distribution due to dense front-end-of-line metal pitch and transistor architectures like RibbonFET and FinFET, which limit the compatibility and efficiency of power delivery methods, particularly for Power Distribution Network (PDN) and Clock-Tree circuits.
Innovation Solution
The implementation of a backside power delivery method using a lead frame bonded to through-silicon via (TSV) pads, which includes a clock tree, power distribution network, and low drop-out linear regulator (LDO) for power management, allowing for disaggregated chiplets and improved thermal via connections to reduce thermal resistance and enhance metal layout efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If front-end-of-line metal pitch is increased to support Power Distribution Network and Clock-Tree circuits, then power delivery capability is improved, but thermal constraints and hot spots worsen due to dense transistor architectures like RibbonFET and FinFET
Solution Approach 1:
The patent introduces a backside power delivery architecture that routes power and ground signals through the substrate backside using through-silicon vias (TSVs) and redistribution layers (RLs). This moves the power distribution path from the traditional front-side planar routing to a three-dimensional path that utilizes the substrate thickness dimension, thereby separating power delivery from the dense front-end metal pitch and reducing thermal congestion at the transistor level.
2Productivity
If transistor density is increased to follow Moore's law, then circuit functionality is improved, but thermal management becomes more difficult due to concentrated heat generation
Solution Approach 1:
The patent extracts the Power Distribution Network and Clock-Tree circuits from the main IC die and implements them as separate chiplets mounted on the substrate backside. This extraction removes the major heat-generating power delivery infrastructure from the dense transistor region, allowing high transistor density to be maintained while thermal management is improved through spatial separation of heat sources.
3Device complexity
If Power Distribution Network and Clock-Tree are integrated on the same die, then device complexity is reduced, but thermal hot spots and power delivery efficiency worsen
Solution Approach 1:
The patent segments the Power Distribution Network and Clock-Tree functionality into separate chiplet components that are independently designed, manufactured, and mounted on the substrate backside. This segmentation allows each chiplet to be optimized for its specific function with dedicated power and ground routing through TSVs, improving power delivery efficiency while maintaining manageable device complexity through modular architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces thermal hotspots and improves RC delays by routing power and ground through redistribution layers and TSVs, enabling more efficient power delivery and thermal management in IC packages, particularly for advanced transistor architectures.
Implementation Method 1
routing power and ground through redistribution layers and TSVs
Implementation Method 2
improved thermal via connections to reduce thermal resistance and enhance metal layout efficiency
Data Source
AI summary
An apparatus having a substrate having first and second substrate contacts; a chip having a front-side chip contact and first and second back-side chip contacts, the front-side chip contact electrically connected to the first substrate contact; a chiplet having a chiplet contact electrically connected the first back-side chip contact; and a lead electrically connected to the second back-side chip contact and electrically connected to the second substrate contact.