Backside Local Interconnect Layout for Non-Overlapping Metal Lines
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Solution Overview
Problem
Current semiconductor chip manufacturing technologies face challenges in efficiently routing power and signal wiring due to limited real estate on the frontside of the chip, as both compete for space, and existing methods struggle to connect source/drain regions of transistors to backside metal lines without direct overlap.
Innovation Solution
The implementation of a backside local interconnect (BLI) that includes a horizontal and vertical portion to connect source/drain regions of transistors to backside metal lines not directly underneath, allowing for flexible power distribution and signal routing by combining direct backside contacts and BLIs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If power and signal wiring are both routed at the frontside of the chip, then complete electrical functionality is achieved, but wiring area real estate becomes severely limited and routing efficiency decreases
Solution Approach 1:
The patent moves the power delivery network from the frontside (2D plane) to the backside of the chip, utilizing the third dimension (depth/thickness) to resolve the wiring space conflict. This allows power lines to occupy the backside metal layers while signal lines remain on the frontside, effectively doubling the available wiring real estate without increasing the chip footprint.
Solution Approach 2:
The wiring network is segmented into two separate systems: frontside signal routing and backside power delivery. This segmentation allows each system to be optimized independently for its specific function, with power lines routed through backside metal layers and signal lines routed through frontside interconnects, eliminating competition for wiring space.
2Adaptability or versatility
If source/drain regions are connected directly to backside metal lines underneath them, then manufacturing is simplified, but flexibility in connecting to multiple metal lines is reduced
Solution Approach 1:
The interconnect structure is made dynamic and configurable through the introduction of local interconnects that can selectively connect source/drain regions to different backside metal lines based on design requirements. Instead of fixed direct connections, the system allows flexible routing configurations where a single source/drain region can connect to multiple metal lines through programmable or design-configurable interconnect paths.
Solution Approach 2:
Local interconnects serve as intermediary elements between source/drain regions and backside metal lines. These intermediaries provide the flexibility to route connections to multiple different metal lines rather than requiring direct underneath connections, enabling adaptable power and signal distribution without significantly increasing overall structural complexity.
3Productivity
If the entire power delivery network is moved to the backside of the chip, then power delivery efficiency increases and frontside signal routing resources are improved, but new interconnect structures are required
Solution Approach 1:
The power delivery network is relocated to the backside of the chip, utilizing the vertical dimension to separate power and signal routing paths. This dimensional separation enables efficient power delivery through dedicated backside metal layers while freeing frontside resources for signal routing, with local interconnects providing the necessary bridging functionality.
Data Source
AI summary
Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a device layer having a frontside and a backside and including a transistor that includes a source/drain region at the backside of the device layer; a first and a second backside metal line with the source/drain region at least partially overlapping vertically with the first backside metal line and not overlapping vertically with the second backside metal line; and a backside local interconnect that conductively connects the source/drain region of the transistor with the second backside metal line, where the backside local interconnect includes a first portion and a second portion, the first portion horizontally extending from an area underneath the source/drain region to an area outside the source/drain region of the transistor, the second portion vertically connecting the first portion to the second backside metal line. Methods for forming the same are also provided.