Backside Logic Interconnect Layout for Denser Signal Routing
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Solution Overview
Problem
The challenge of reducing the size of memory and logic cells in integrated circuits while efficiently routing logic signals between transistor elements is hindered by crowded metal lines and parasitic effects, leading to inefficient use of space in the interconnect region.
Innovation Solution
Implementing backside interconnect structures that connect transistor source or drain regions, replacing frontside local interconnect layers to free up space for metal 0 signal tracks, using conductive materials like tungsten, titanium, tantalum, ruthenium, or molybdenum, and forming non-linear shapes such as an 'L' shape to connect misaligned regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If frontside local interconnect layers are used to route logic signals between transistor elements, then signal routing is achieved, but space utilization becomes inefficient and parasitic effects increase
Solution Approach 1:
The patent moves the interconnect structure from the frontside (original plane) to the backside (opposite side of the substrate), effectively utilizing another dimension of the substrate to route logic signals. This dimensional transition allows signal routing without occupying frontside interconnect region space, thereby resolving the space utilization problem while maintaining routing capability.
Solution Approach 2:
Instead of routing signals from the frontside of the substrate as conventionally done, the patent inverts the approach by routing signals from the backside. This inversion allows the interconnect structure to be formed on the opposite side of the substrate, freeing up frontside space and reducing parasitic effects associated with crowded metal lines.
2Productivity
If device spacing at the device layer is reduced to increase integration density, then more devices can be packed, but routing becomes more difficult and parasitic effects increase
Solution Approach 1:
By transitioning the interconnect routing to the backside of the substrate, the patent enables closer device spacing at the device layer without proportionally increasing routing complexity. The backside interconnect structure provides a separate routing plane that does not interfere with frontside device placement, allowing higher integration density while maintaining manageable routing complexity.
3Adaptability or versatility
If more metal lines are added to route multiple logic signals, then signal routing capability is improved, but parasitic effects increase and space efficiency decreases
Solution Approach 1:
The patent utilizes the backside of the substrate as a separate routing dimension, allowing multiple logic signals to be routed without adding crowded metal lines to the frontside. This dimensional separation enables versatile signal routing capability while avoiding the parasitic effects that result from dense metal line configurations on the same plane.
Data Source
AI summary
Techniques are provided herein to form an integrated circuit having a backside interconnect structure coupled between different transistor source or drain regions. The backside interconnect structure may be used to replace frontside local interconnect structures, thus freeing up more space in the frontside interconnect region. A first semiconductor device includes a first semiconductor region extending between a first source or drain region and a second source or drain region, and a second semiconductor device includes a second semiconductor region extending between a third source or drain region and a fourth source or drain region. Each of the source or drain regions have corresponding backside contacts coupled to a bottom surface of the source or drain region. A backside conductive layer may extend beneath the semiconductor devices and be coupled to any of the backside contacts to provide connection between the corresponding source or drain regions.