Semiconductor transistor device having backside source/drain contact with a low-k spacer and method of forming the same
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Solution Overview
Problem
As semiconductor devices shrink, the close proximity of source/drain contacts and gate contacts increases parasitic capacitance, reducing process windows and impacting device performance and switching speed.
Innovation Solution
A method is introduced to form backside source/drain contacts spaced apart from adjacent structures by a gap, reducing parasitic capacitance by forming a gap between the backside source contact and the gate structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If contact features are packed closely on one side of the substrate, then packing density is improved, but parasitic capacitance between backside contacts and gate structures increases
Solution Approach 1:
The patent moves routing features from the front side to the backside of the substrate, utilizing the third dimension (depth/thickness) to resolve the contradiction. By forming backside power rails and backside contacts on the opposite side of the substrate from the gate structures, the design achieves high packing density while maintaining physical separation that reduces parasitic capacitance between contacts and gates.
2Productivity
If geometry size is reduced to increase functional density, then production efficiency is improved, but process window for contact formation is reduced
Solution Approach 1:
The patent segments the contact formation process into multiple stages with intermediate structures. A mandrel structure is formed first, followed by deposition of a first dielectric material, then a second dielectric material, and finally removal of the mandrel. This segmented approach allows each step to be optimized independently, maintaining process windows even as overall geometry dimensions shrink.
Solution Approach 2:
The mandrel structure is formed in advance before the actual contact features are created. This preliminary structure serves as a template that defines the eventual contact positions and dimensions, allowing subsequent processing steps to be performed with greater precision and larger process windows, even at reduced geometry sizes.
Data Source
AI summary
A semiconductor structure includes a channel member, a gate structure disposed over the channel member, a source/drain feature connected to the channel member and adjacent to the gate structure, a source/drain contact disposed below and connected to the source/drain feature, a backside dielectric feature disposed below the channel member, and a first dielectric layer and a second dielectric layer disposed between the backside dielectric feature and the source/drain contact. The first dielectric layer includes a low-k dielectric material.