Backside Memory Cell Integration for Low-Resistance Semiconductor Layouts
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Solution Overview
Problem
Current integrated circuit manufacturing processes for data storage elements like MRAM face challenges in efficiently integrating memory cells within tightly-packed arrays without increasing die area, and in minimizing thermal budgets and routing resistance.
Innovation Solution
The process involves forming a semiconductor device with a bulk semiconductor substrate, active devices, and interconnect structures on both sides of the substrate, where memory cells are embedded in the backside interconnect structure to reduce thermal exposure and enhance performance, while also allowing for dual memory cell placement on both sides of the substrate to increase capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If memory cells are placed in tightly-packed arrays to minimize die area, then die area is reduced, but thermal budgets increase and routing resistance increases
Solution Approach 1:
The patent utilizes both front and back sides of the semiconductor substrate for memory cell placement, transitioning from a single-sided (2D) layout to a dual-sided (3D) architecture. This dimensional change allows memory cells to be distributed across both surfaces of the substrate, reducing the density and thermal concentration on each side while maintaining high overall capacity without increasing die area.
2Area of stationary object
If memory cells are placed in tightly-packed arrays to minimize die area, then die area is reduced, but routing resistance increases
Solution Approach 1:
By distributing memory cells across both front and back sides of the substrate, the patent reduces the routing distance and complexity. Interconnect structures can be optimized on each side independently, and the conductive vias penetrating through the substrate provide direct vertical connections, reducing overall routing resistance compared to a single-sided tightly-packed array.
3Temperature
If memory cells are embedded in backside interconnect structure, then thermal budgets are reduced and performance is enhanced, but device complexity increases
Solution Approach 1:
The patent divides the memory device into two separate segments: front-side memory cells and back-side memory cells, each with their own interconnect structures. This segmentation allows independent optimization of thermal management and interconnect design on each side, reducing the thermal budgets for each segment while the overall device complexity is managed through modular architecture.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, an interconnect structure, a memory cell and a conductive via. The semiconductor substrate has a first side and a second side opposite to the first side. The gate structure is disposed over the first side of the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate aside the gate structure. The interconnect structure is disposed over the first side of the semiconductor substrate and electrically connected to the source region. The memory cell is disposed over the second side of the semiconductor substrate and electrically connected to the drain region. The conductive via is disposed in the semiconductor substrate between the drain region and the memory cell and electrically connects the drain region and the memory cell.