Backside Memory Layout With Vertical Power Rails and Logic Separation
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Solution Overview
Problem
Existing semiconductor device fabrication processes face challenges in integrating more memory cells within a given area due to the increasing difficulty in reducing transistor dimensions and the complexity of forming interconnect structures, memory cells, and power rails in the same space.
Innovation Solution
The semiconductor device is designed with a logic portion and a memory portion, where the logic portion is formed on the frontside of a substrate and the memory portion is formed on the backside. Vertically disposed power rails are used to supply voltages to both portions, allowing for a more compact design and enabling further reduction in transistor dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistor dimensions are continuously reduced to increase integration density, then more components can be integrated into a given area, but manufacturing precision and device reliability deteriorate due to increasing difficulty in reducing transistor dimensions
Solution Approach 1:
The patent transitions from planar 2D transistor layouts to three-dimensional vertical channel structures (nanosheets, nanowires, GAA FETs). By stacking multiple thin semiconductor layers vertically to form channels that extend through the substrate, the design achieves higher integration density without further reducing lateral feature sizes. This vertical dimensionality change allows continued scaling while maintaining manufacturable transistor dimensions.
2Quantity of substance
If interconnect structures, memory cells, and power rails are formed in the same space to increase integration density, then more components are integrated into a given area, but device complexity increases
Solution Approach 1:
The patent divides the semiconductor device into distinct functional segments: logic portions with transistor arrays, memory portions with storage elements, and vertically separated power rail structures. Each segment is independently formed and optimized, then integrated through the substrate. This segmentation allows complex functionality to be achieved while maintaining manageable structural complexity through modular design.
Solution Approach 2:
The patent utilizes vertical stacking to separate different functional components along the depth axis. Power rails are formed as vertical structures extending through the substrate, memory cells are stacked above logic portions, and interconnect layers are arranged in three-dimensional space. This vertical dimensionality resolves the conflict between high integration density and structural complexity by organizing components in the third dimension rather than competing for planar space.
3Reliability
If power rails are vertically disposed to supply voltages to logic and memory portions, then voltage drop is reduced and device performance improves, but manufacturing complexity increases
Solution Approach 1:
The patent implements power delivery by forming vertical power rail structures that extend through the substrate depth, connecting to logic and memory portions at different vertical levels. This vertical power rail architecture reduces voltage drop by providing direct, short current paths from power sources to distributed load points, eliminating the need for long lateral power traces. The vertical dimensionality of power delivery simplifies the overall power distribution network while improving electrical performance.
Data Source
AI summary
A semiconductor device includes a first transistor formed on a first side of a substrate. The semiconductor device includes a first power rail structure vertically disposed over the first transistor, a second power rail structure vertically disposed over the first power rail structure, and a memory portion vertically disposed over the second power rail structure. The first power rail structure, and a second power rail structure, and the memory portion are all disposed on a second side of the substrate opposite to the first side.