Backside Memory Layout for Nanosheet FET Signal Path Reduction
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Solution Overview
Problem
Conventional integrated circuits face challenges in device density and signal efficiency due to the physical and electrical limitations of arranging memory structures between interconnect wires and transistors, leading to increased height and inefficient signal travel.
Innovation Solution
The integration of nanosheet field effect transistors (NSFETs) with a contact plug structure directly coupling memory structures to transistors, and a second interconnect structure above the memory, reduces vertical interconnect dimensions and signal distance, enhancing device density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory structures are arranged between interconnect wires and transistors in conventional integrated circuits, then the circuit functionality is achieved, but the overall height of the chip increases and device density decreases
Solution Approach 1:
The patent applies backside integration to move memory structures from the conventional planar arrangement (between interconnect and transistor on the same layer) to a vertical arrangement on the opposite side of the substrate. This dimensional reorganization allows memory to be coupled to transistors through vertical vias from the backside, reducing the horizontal footprint and increasing device density without compromising functionality.
2Reliability
If memory structures are arranged between interconnect wires and transistors, then the circuit is functional, but the signal travel distance increases and signal efficiency decreases
Solution Approach 1:
The patent extracts the memory structures from the congested interconnect region and relocates them to the backside of the substrate. This separation removes the bottleneck where memory was previously positioned between interconnect wires and transistors, allowing for optimized signal paths with reduced travel distance and improved signal efficiency.
3Ease of manufacture
If conventional memory arrangement is used between interconnect and transistor, then manufacturing is straightforward, but the vertical interconnect dimensions increase
Solution Approach 1:
The patent inverts the conventional manufacturing sequence by forming memory structures on the backside of the substrate after the frontside processing is complete. This reverse approach allows standard frontside CMOS processing to proceed unchanged, while memory is added subsequently through backside thinning, patterning, and via formation, thereby maintaining manufacturing simplicity while reducing vertical interconnect dimensions.
Data Source
AI summary
In some embodiments, the present disclosure relates to an integrated chip that includes a first and second transistors arranged over a substrate. The first transistor includes first channel structures extending between first and second source/drain regions. A first gate electrode is arranged between the first channel structures, and a first protection layer is arranged over a topmost one of the first channel structures. The second transistor includes second channel structures extending between the second source/drain region and a third source/drain region. A second gate electrode is arranged between the second channel structures, and a second protection layer is arranged over a topmost one of the second channel structures. The integrated chip further includes a first interconnect structure arranged between the substrate and the first and second channel structures, and a contact plug structure coupled to the second source/drain region and arranged above the first and second gate electrodes.