Backside Memory Over NSFET Contact Plugs for Dense Chip Layouts
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Solution Overview
Problem
Conventional integrated circuits face challenges in reducing the height of the device due to the arrangement of memory structures between interconnect wires, which decreases device density and increases signal travel distance, leading to inefficiencies.
Innovation Solution
The proposed solution involves arranging a memory structure directly over and electrically coupled to a contact plug structure, which is in turn coupled to nanosheet field effect transistors (NSFETs), thereby reducing the vertical dimension of interconnect structures and minimizing signal travel distance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory structures are arranged between interconnect wires, then device density is improved, but the height of the device increases and signal travel distance increases
Solution Approach 1:
The patent transitions from a planar arrangement where memory structures are positioned between interconnect wires to a vertical arrangement where memory structures are stacked directly over transistors. This dimensional change allows memory to be integrated in the vertical direction, reducing the horizontal footprint and improving device density without proportionally increasing overall device height.
Solution Approach 2:
The patent implements a nested structure where memory structures are positioned directly over transistor structures, with interconnect structures integrating both levels. This nesting approach allows multiple functional elements to occupy overlapping vertical spaces, effectively packing more functionality into a compact volume and improving device density.
2Quantity of substance
If memory structures are arranged between interconnect wires, then device density is improved, but signal travel distance increases
Solution Approach 1:
By moving memory structures vertically over transistors rather than horizontally between interconnect wires, the patent creates direct vertical pathways for signal transmission. This reduces the lateral distance signals must travel and enables shorter interconnect paths, improving signal travel efficiency while maintaining high device density.
Solution Approach 2:
The patent introduces contact plug structures as intermediaries that directly connect transistor source/drain regions to memory structures. These contact plugs eliminate the need for lengthy lateral interconnect paths through the interconnect wire network, providing direct vertical signal pathways that reduce signal travel distance while maintaining compact device footprint.
3Length of moving object
If memory structures are arranged directly over transistors, then signal travel distance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent divides the integrated circuit into distinct functional segments: transistor structures at the first level, memory structures at the second level, and interconnect structures that integrate both levels. This segmentation allows each component to be optimized and manufactured separately using specialized processes, then combined through bonding, reducing overall manufacturing complexity despite the three-dimensional architecture.
Solution Approach 2:
The patent employs preliminary actions by forming transistor structures and memory structures separately on different substrates or wafer segments before final integration. Contact plug structures are prepared in advance with appropriate materials and geometries to facilitate direct vertical connections. This preliminary preparation simplifies the final assembly process and reduces manufacturing complexity.
Data Source
AI summary
In some embodiments, the present disclosure relates to an integrated chip that includes a first and second transistors arranged over a substrate. The first transistor includes first channel structures extending between first and second source/drain regions. A first gate electrode is arranged between the first channel structures, and a first protection layer is arranged over a topmost one of the first channel structures. The second transistor includes second channel structures extending between the second source/drain region and a third source/drain region. A second gate electrode is arranged between the second channel structures, and a second protection layer is arranged over a topmost one of the second channel structures. The integrated chip further includes a first interconnect structure arranged between the substrate and the first and second channel structures, and a contact plug structure coupled to the second source/drain region and arranged above the first and second gate electrodes.