Backside Wafer Memory Cell Layout for Shorter Signal Routing
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Solution Overview
Problem
As the number of metal interconnect and metal layers between memory cells and logic devices increases, signal routing time and resistance also increase, slowing down operations.
Innovation Solution
Forming memory cells on the backside of a substrate with a buried metal structure and through silicon via (TSV) connections to reduce routing distance and metal interconnect layers, utilizing TSVs and buried metal structures for current routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory cells are formed on top of multiple metal interconnects and metal layers, then the memory cell can be connected to logic devices, but the routing distance and resistance increase, slowing down signal routing
Solution Approach 1:
The patent inverts the conventional stacking order by forming memory cells on the backside of the substrate rather than on top of multiple metal interconnect layers on the frontside. This inversion reduces the routing distance between memory cells and logic devices by utilizing through-substrate vias (TSVs) and buried metal structures, directly addressing the contradiction between connection capability and routing distance.
Solution Approach 2:
The patent transitions from a planar routing approach (horizontal metal interconnect layers) to a three-dimensional approach using vertical through-substrate vias and buried metal structures. This dimensional change allows signals to route through the substrate thickness rather than traversing multiple horizontal metal layers, reducing overall routing distance and resistance.
2Reliability
If the number of metal interconnect and metal layers between memory cell and logic devices increases, then connectivity is improved, but resistance increases and signal routing slows down
Solution Approach 1:
By inverting the conventional architecture and placing memory cells on the backside of the substrate, the patent reduces the number of metal interconnect layers that signals must traverse. Instead of passing through multiple horizontal metal layers on the frontside, signals use vertical TSVs and fewer metal layers on the backside, thereby reducing both the quantity of metal interconnect and the associated resistance.
Solution Approach 2:
The patent segments the interconnection path into distinct functional regions: frontside logic devices, through-substrate vias (TSVs) for vertical penetration, buried metal structures within the substrate, and backside metal layers for memory cell interconnection. This segmentation allows optimization of each segment, reducing the total number of metal interconnect layers required while maintaining connectivity.
Data Source
AI summary
A memory cell in a backside of a wafer and methods of forming the memory cell are described. A buried metal structure can be formed through a frontside of a substrate. At least one device can be formed on the frontside of a substrate, where the at least one device can be connected to the buried metal structure in the substrate. A through silicon via (TSV) can be formed through a backside of the substrate, where the TSV can be connected to the buried metal structure. A memory cell can be formed on the backside of the substrate, where the memory cell can be connected to the TSV.