Backside-Contact Memory Access Transistor Layout for Cell Scaling
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Solution Overview
Problem
The scaling of multi-gate and nanowire transistors in integrated circuits poses challenges in maintaining mobility and short channel control, particularly due to constraints on lithographic processes, and there is a need for high bandwidth computing solutions that optimize device performance.
Innovation Solution
The implementation of integrated circuit structures with backside contacts, which include fin-based or nanowire-based memory layers, allows for reduced cell area and efficient access to transistors, enabling high bandwidth devices that can operate at low temperatures through the use of conductive contacts and conductive vias, and employing double-sided device processing methods to facilitate backside access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional lithographic processes are used to pattern transistors, then feature size can be reduced, but spacing between features becomes insufficient
Solution Approach 1:
The patent applies dimensionality change by moving contacts from the front side to the back side of the transistor structure. This spatial reconfiguration allows bitline and storage node contacts to be formed on opposite sides of the device, eliminating the need for overlapping contacts on the same plane and resolving the lithographic spacing constraint
2Quantity of substance
If transistor dimensions are scaled down to increase density, then capacity increases, but performance optimization becomes increasingly difficult
Solution Approach 1:
The patent segments the contact structure into separate front-side and back-side components. By dividing the contact formation process and location, the design achieves higher density while maintaining simplified individual contact structures that are easier to optimize for performance
3Area of stationary object
If bitline and storage node contacts overlap on the front side, then device density increases, but lithographic patterning becomes impossible
Solution Approach 1:
The patent resolves the patterning impossibility by transitioning from two-dimensional overlapping contacts to three-dimensional separated contacts. Bitline contacts are formed on the front side while storage node contacts are formed on the back side, allowing both contacts to coexist without overlapping and enabling standard lithographic processes to be used
Data Source
AI summary
Structures having memory access transistors with backside contacts are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a fin-based transistor, and a capacitor structure above the fin-based transistor of the device layer. A backside structure is below the front-side structure. The backside structure includes a conductive contact electrically connected to the fin-based transistor of the device layer.