Backside Programmable Memory Via Layout for Faster Design Changes
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Solution Overview
Problem
Current semiconductor fabrication methods face challenges in efficiently managing the power delivery network (PDN) as device densities increase, particularly in scaling backside power delivery architectures, which requires iterative processes and long time-to-market for design changes.
Innovation Solution
The implementation of a backside programmable memory structure that allows for the customization of memory cells by metallizing or disconnecting placeholder backside vias, enabling programming without requiring new frontside masks, thus separating the frontside and backside fabrication processes and reducing the need for iterative redesign.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If backside power delivery architecture is implemented to improve power delivery network efficiency, then power delivery capability is improved, but design change time increases due to iterative processes
Solution Approach 1:
The patent segments the memory array into multiple independently programmable banks, where each bank can be individually configured through backside vias. This allows selective programming of specific banks without affecting others, enabling partial redesign and reducing overall design change time while maintaining improved power delivery architecture.
Solution Approach 2:
The patent implements placeholder backside vias during frontside fabrication that can be selectively metallized in later stages. This preliminary preparation allows rapid design changes by simply adding or removing metallization connections to pre-positioned vias, eliminating the need to restart frontside fabrication and significantly reducing design change time.
2Adaptability or versatility
If iterative fabrication processes are used for design changes, then manufacturing flexibility is improved, but time-to-market increases
Solution Approach 1:
The patent prepares placeholder backside vias during frontside fabrication that remain dormant until needed. This preliminary action enables rapid design iterations by allowing manufacturers to simply add metallization layers to connect to specific vias without restarting the entire fabrication process, thus maintaining flexibility while accelerating time-to-market.
Solution Approach 2:
The patent inverts the traditional fabrication sequence by preparing all via structures during frontside fabrication but delaying the metallization decision to a later stage. This inversion allows design changes to be made after frontside processing is complete, enabling flexible customization without requiring iterative frontside fabrication cycles.
3Ease of manufacture
If non-trusted foundries are used for bulk fabrication, then manufacturing cost is reduced, but security and customization capability are compromised
Solution Approach 1:
The patent segments the programming function into independent backside via connections that can be selectively activated. This segmentation allows trusted foundries to perform secure metallization operations on specific banks after shipping wafers to non-trusted foundries for bulk fabrication, maintaining security requirements while enabling cost-effective manufacturing.
Solution Approach 2:
The patent prepares all via structures and placeholder connections during frontside fabrication at trusted facilities, establishing secure architectural foundations before wafers are shipped to non-trusted foundries for bulk BEOL processing. This preliminary action separates security-critical operations from cost-sensitive bulk manufacturing.
Data Source
AI summary
Embodiments of the present invention are directed to processing methods and resulting structures having backside programmable memory cells. In a non-limiting embodiment, a front end of line structure having a plurality of programmable cells is formed such that each programmable cell includes a backside via in direct contact with a device region of the respective cell. A first portion of the backside vias defines one or more placeholder backside vias and a second portion defines one or more programmed backside vias. A back end of line structure (word line) is formed on a first surface of the front end of line structure. A backside structure is formed on a second surface of the front end of line structure opposite the first surface. The backside structure includes a backside metallization layer (bit line) in direct contact with the one or more programmed backside vias.