Backside Bulk Silicon MEMS Integration on IC Dies
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Solution Overview
Problem
The backside surface of integrated circuit (IC) dies is typically unused, limiting the potential for additional functional integration and efficiency in semiconductor devices.
Innovation Solution
The implementation of a process to form microelectromechanical systems (MEMS) devices and through-silicon vias (TSVs) on the backside of IC chips, enabling the integration of MEMS devices and improved connectivity with other substrates, such as memory modules, by using techniques like anisotropic etching and metal deposition processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the backside surface of IC die is left unused as conventional practice, then the manufacturing process remains simple, but the functional integration and efficiency of semiconductor devices are limited
Solution Approach 1:
The patent utilizes the backside surface of the IC die, which is the opposite dimension from the frontside where active devices are formed. By forming MEMS devices and TSVs on the backside surface, the invention effectively adds another functional dimension to the semiconductor device, enabling additional functionality without interfering with the frontside circuitry.
Solution Approach 2:
The backside surface of the IC die is transformed from a non-functional surface to a multi-functional surface that can host MEMS devices, TSVs, and other functional structures. This allows the same substrate to serve multiple purposes: frontside for active circuitry and backside for sensors, actuators, and interconnect structures.
2Reliability
If MEMS devices and TSVs are formed on the backside of IC chips, then interconnectivity and functionality are enhanced, but the manufacturing process becomes more complex
Solution Approach 1:
The patent performs preliminary actions by forming the MEMS devices and TSVs on the backside surface during the same manufacturing process sequence as the frontside devices. This includes forming sacrificial layers, patterning, depositing materials, and etching TSVs through the substrate, all integrated into the existing CMOS fabrication process flow.
Solution Approach 2:
The invention merges the formation of frontside active devices and backside MEMS/TSV structures into a single integrated manufacturing process. By combining these operations and using shared process steps (such as deposition, etching, and patterning), the patent achieves enhanced functionality without proportionally increasing manufacturing complexity.
3Productivity
If the backside surface is utilized for MEMS devices, then the efficiency and capabilities of semiconductor devices increase, but the device structure becomes more complex
Solution Approach 1:
The patent implements nesting by placing MEMS devices and TSVs on the backside surface of the IC die, effectively nesting additional functional structures within the existing substrate structure. The TSVs pass through the substrate to connect frontside and backside structures, creating a nested three-dimensional integration architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the utilization of previously unused backside surfaces for functional integration, enhancing the performance and functionality of IC chips by enabling the formation of MEMS devices and improved interconnectivity, thereby increasing the efficiency and capabilities of semiconductor devices.
Implementation Method 1
by using techniques like anisotropic etching and metal deposition processes
Implementation Method 2
by using techniques like anisotropic etching and metal deposition processes
Data Source
AI summary
An integrated circuit device that comprises a single semiconductor substrate, a device layer formed on a frontside of the single semiconductor substrate, a redistribution layer formed on a backside of the single semiconductor substrate, a through silicon via (TSV) formed within the single semiconductor substrate that is electrically coupled to the device layer and to the redistribution layer, a logic-memory interface (LMI) formed on a backside of the single semiconductor substrate that is electrically coupled to the redistribution layer, and a MEMS device formed on the backside of the single semiconductor substrate that is electrically coupled to the redistribution layer.