Backside Metal Layer Edge Profile for Semiconductor Mounting
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Solution Overview
Problem
During the singulation of semiconductor wafers, ductile metal layers on the backside can form burrs that protrude and interfere with the mounting process, causing voids and adverse chemical reactions with solder.
Innovation Solution
A semiconductor device design where the peripheral part of the metal layer at the edge of the substrate extends towards the major surface, preventing burrs from interfering with mounting and minimizing exposure of underlying metal layers to solder.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ductile metal layers are used in backside metallisation, then electrical conductivity and mechanical strength are improved, but burrs are formed during singulation that interfere with mounting
Solution Approach 1:
The harmful burrs are removed from the metal layer peripheral parts through a chemical etching process. The etching solution selectively removes the ductile metal material from the edges, preventing burr formation while preserving the bulk metal layer properties. This extraction of the harmful component allows the use of ductile metals without the mounting interference problem.
Solution Approach 2:
The peripheral parts of the metal layers are chemically etched and removed before the singulation process. This preliminary action eliminates the source of burr formation, so that when singulation occurs, no burrs are generated from the metal layers. The etching step is performed in advance to prevent the harmful effect rather than correcting it afterward.
2Reliability
If metal layers extend to the edge of the substrate, then electrical contact is improved, but underlying metal layers are exposed to solder causing adverse chemical reactions
Solution Approach 1:
The peripheral parts of the metal layers are removed by chemical etching, creating a recessed configuration. This extraction ensures that even when metal layers extend toward the substrate edge, the exposed peripheral portions are eliminated, preventing solder from contacting and reacting with the underlying metal layers during the mounting process.
Solution Approach 2:
The metal layer configuration is changed from a flat two-dimensional extension to a three-dimensional recessed structure. By removing the peripheral parts, the metal layers form a stepped or recessed profile, which adds a vertical dimension to the design. This dimensional change allows the metal layers to provide electrical contact while preventing solder exposure to underlying layers.
3Strength
If thicker metal layers are used, then mechanical strength is improved, but burr formation and exposure to solder is worsened
Solution Approach 1:
The chemical etching process selectively removes only the peripheral parts of the metal layers, leaving the central and thicker portions intact. This extraction approach maintains the mechanical strength provided by the bulk metal material while eliminating the problematic thin peripheral regions that generate burrs during singulation.
Solution Approach 2:
Different regions of the metal layer are treated differently: the peripheral parts are chemically etched and removed, while the central and thicker regions are preserved to maintain mechanical strength. This local differentiation allows the structure to have both the strength of thick metal layers and the burr-free characteristic of thinned edges.
Data Source
AI summary
A semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface, a backside and side surfaces extending between the major surface and the backside. The semiconductor device also includes at least one metal layer extending across the backside of the substrate. A peripheral part of the at least one metal layer located at the edge of the substrate between the backside and at least one of the side surfaces extends towards a plane containing the major surface. This can prevent burrs located at the peripheral part of the at least one metal layer interfering with the mounting of the backside of the substrate on the surface of a carrier.