Backside Metal Mirror Grating Couplers for CMOS-Compatible Silicon Photonics
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Solution Overview
Problem
The dimensional mismatch between single-mode optical fibers and silicon photonic integrated circuits on silicon-on-insulator wafers results in high coupling losses, and existing methods to enhance coupling efficiency are technologically complex and not fully CMOS compatible.
Innovation Solution
The method involves structuring grating couplers on a semiconductor-on-insulator wafer with a backside mirror layer deposited in membrane windows, using a standard CMOS-compatible process that does not require additional wafer bonding, enhancing coupling efficiency by matching the diffracted field to the Gaussian mode profile of the fiber.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If grating couplers are structured in the front silicon-on-insulator layer, then coupling between optical fibers and nanophotonic waveguides is enabled, but coupling efficiency remains low (about 30%)
Solution Approach 1:
The patent introduces a backside mirror layer positioned at a specific depth below the grating coupler structure. This adds a vertical dimension to the coupling mechanism, allowing light to be reflected upward from the substrate backside, thereby redirecting diffracted power that would otherwise be lost and improving coupling efficiency without complicating the front-side grating structure
Solution Approach 2:
The patent introduces a polymer layer as an intermediary medium between the grating coupler and the optical fiber. This polymer layer with refractive index n=1.50 matches the Gaussian mode profile of the fiber, serving as a mediator that facilitates more efficient mode matching and light coupling between the grating structure and the fiber core
2Loss of energy
If a gold bottom mirror is added to enhance coupling efficiency, then coupling efficiency improves to 69%, but the fabrication process becomes complex and not CMOS compatible
Solution Approach 1:
The patent changes the material parameter from gold to aluminum for the backside mirror layer. Aluminum can be deposited using standard sputtering techniques that are CMOS compatible, whereas gold deposition followed by substrate thinning and wafer bonding is not. This material substitution maintains the optical reflection function while enabling standard semiconductor fabrication processes
Solution Approach 2:
The patent performs the mirror layer deposition on the complete wafer before dicing into individual devices. This preliminary action allows the mirror layer to be formed continuously across the entire wafer surface in a single step, avoiding the need for subsequent alignment and deposition steps on each individual device, thereby simplifying the overall fabrication process
3Loss of energy
If the substrate is thinned and gold mirror is deposited, then coupling efficiency increases, but additional wafer bonding and buffer layer processes are required
Solution Approach 1:
The patent extracts the mirror layer formation step from the complex sequence of substrate thinning, gold deposition, and wafer bonding. By depositing the aluminum mirror layer on the complete wafer before dicing, the method eliminates the need for subsequent wafer bonding and buffer layer processes, reducing the total number of fabrication steps while maintaining high coupling efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly enhances coupling efficiency while being technologically simple and cost-effective, maintaining CMOS compatibility, allowing for efficient light transfer between single-mode fibers and photonic integrated circuits.
Implementation Method 1
One way to ensure good broadband coupling efficiency between single mode fibers and silicon photonic integrated circuits has been presented in the last years using Bragg structures called grating couplers
Implementation Method 2
It has been proposed to enhance the coupling efficiency by redirecting the diffracted power toward the substrate back to the silicon waveguide
Data Source
AI summary
The invention generally relates to grating couplers based on silicon-on-insulator technology. On the back side of the wafer membrane windows are etched extending to the buried oxide layer of the SOI wafer and a mirror layer is then deposited within the membrane windows on the back side of the buried oxide layer.