Backside Metallization for FPGA Clock Routing
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Solution Overview
Problem
High-capacity integrated circuits, such as FPGAs, face challenges with power consumption and signal integrity due to multiple clocks and communication wires, which lead to significant power consumption, clock skew, and jitter, and current manufacturing processes are complex and costly.
Innovation Solution
Implementing backside metallization by separating the integrated circuit into a first layer for signal transfer and a second layer for clock routing, power delivery, and other functionalities, reducing the distance between clock resources and power supply, and standardizing the first layer to simplify manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple clocks and communication wires are added to improve integrated circuit functionality, then device capability is enhanced, but power consumption increases significantly
Solution Approach 1:
The patent divides the integrated circuit into two separate layers: a first layer dedicated to signal transfer and a second layer dedicated to power delivery and clock routing. This segmentation allows each layer to be optimized independently, reducing interference and improving overall efficiency while maintaining enhanced device capability.
Solution Approach 2:
The patent transitions from a planar single-layer design to a three-dimensional stacked architecture by utilizing vertical stacking of functional layers. This dimensional change enables simultaneous optimization of signal routing and power delivery without increasing lateral footprint, thereby maintaining capability while reducing power consumption through shorter interconnect paths.
2Adaptability or versatility
If multiple clocks and communication wires are added to improve integrated circuit functionality, then device capability is enhanced, but clock skew and jitter increase
Solution Approach 1:
By separating clock routing to a dedicated second layer, the patent isolates clock signals from data signals in the first layer. This eliminates capacitive coupling and crosstalk between signal types, thereby reducing clock skew and jitter while preserving enhanced device capability.
Solution Approach 2:
The patent introduces a dedicated clock routing layer as an intermediary between the signal transfer layer and the clock sources. This intermediate layer provides specialized routing paths with controlled impedance and minimal interference, improving clock signal integrity without limiting device capability.
3Ease of manufacture
If conventional single-layer manufacturing is used, then manufacturing process is simpler, but manufacturing cost and complexity increase for high-capacity circuits
Solution Approach 1:
The patent segments the manufacturing process into two independent stages: fabricating the first layer with signal transfer components, then fabricating the second layer with power and clock components, and finally bonding the layers together. This segmentation allows each layer to be manufactured using standardized processes, reducing overall complexity and cost for high-capacity circuits.
Solution Approach 2:
The patent adopts a three-dimensional stacked manufacturing approach, building the circuit vertically rather than horizontally. This enables independent optimization of each layer's manufacturing process and allows parallel fabrication of multiple layers, thereby reducing total manufacturing complexity and cost despite the added vertical dimension.
4Device complexity
If clock routing is integrated with signal transfer in the same layer, then device structure is simpler, but clock skew and power consumption increase
Solution Approach 1:
The patent segments the device structure into two functional layers: the first layer handles signal transfer while the second layer handles clock routing and power delivery. This segmentation physically separates clock signals from data signals, eliminating capacitive coupling and reducing clock skew, while the modular design maintains overall structural simplicity.
5Device complexity
If power delivery and signal transfer share the same layer, then device structure is simpler, but power consumption and signal interference increase
Solution Approach 1:
The patent segments power delivery and signal transfer into separate layers. The second layer is dedicated to power delivery circuitry and wide power buses, while the first layer handles signal transfer. This separation reduces resistive losses in power paths and minimizes capacitive loading on signal lines, thereby reducing overall power consumption while maintaining structural simplicity through modular layering.
Data Source
AI summary
A programmable logic device may include a first layer formed using backside metallization on a back plane of the programmable logic device and a second fabric routing circuitry to route second data within the programmable fabric. The first layer may include first fabric routing circuitry to route first data within a programmable fabric of the programmable logic device, and clock routing circuitry to route clock signals within the programmable fabric.