Backside Metallization and Buried Rails for Low-Skew Clock Routing
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Solution Overview
Problem
Increased resistance in interconnects and vias due to miniaturization in integrated circuits leads to significant clock skew variation and timing uncertainties, necessitating improved clock distribution methods.
Innovation Solution
Employing buried rails and backside metals for signal distribution, eliminating the need for frontside interconnections and reducing routing congestion, thereby minimizing clock timing uncertainties and area penalties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If miniaturization of components is pursued to advance computing power, then component density and integration are improved, but resistance of interconnects and vias increases causing clock skew variation
Solution Approach 1:
The patent introduces backside metallization layers (BL0, BL1, BL2) on the substrate backside and buried rails extending from frontside to backside, utilizing the third dimension (vertical depth) to create additional signal distribution pathways. This dimensional expansion allows clock signals to be distributed through multiple layers without increasing lateral interconnect resistance, thereby maintaining timing reliability while supporting higher component density.
2Ease of operation
If conventional frontside interconnections are used for signal distribution, then routing is straightforward, but routing congestion and area penalties increase
Solution Approach 1:
The patent divides the signal distribution function into multiple independent layers: frontside metallization layers (ML0-ML3) for local routing, backside metallization layers (BL0-BL2) for global distribution, and buried rails for vertical inter-layer connections. This segmentation allows each layer to be optimized independently, reducing routing congestion on the frontside while maintaining design simplicity through standardized inter-layer via connections.
3Ease of manufacture
If standard interconnect structures are used, then manufacturing is simple, but clock timing uncertainties increase due to resistance variations
Solution Approach 1:
The patent employs composite interconnect structures combining multiple metal layers with different properties: copper or cobalt-filled vias for vertical connections, tungsten plugs for low-resistance contacts, and various dielectric materials (BSG, BSG2, CMP) for insulation and planarization. This composite approach reduces overall interconnect resistance and timing uncertainty while maintaining compatibility with existing CMOS fabrication processes through standardized deposition and etching techniques.
Data Source
AI summary
Disclosed are integrated circuit structures with buried rails and backside metals for routing input signals to and/or output signals from one or more cells of the integrated circuit structures. Port landing-free connections to input ports and/or from output ports are enabled. As a result, signal routing flexibility is enhanced.