Backside Metallization Layout for Low-Noise Power Delivery
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Solution Overview
Problem
Conventional semiconductor technologies face challenges in efficiently forming backside power delivery networks with reduced parasitic capacitance and power supply noise, requiring complex via patterning that increases fabrication steps.
Innovation Solution
The implementation of a semiconductor structure with backside metallization layers that eliminate via connections between metal lines, allowing power and ground rails to be formed in backside metallization levels, utilizing perpendicular orientations and high-k dielectric barriers to increase decoupling capacitance and reduce power supply noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If via patterning is used to connect metallization layers, then electrical connection between layers is achieved, but fabrication complexity and number of steps increase
Solution Approach 1:
The patent extracts and eliminates the via connection structure from the metallization layer assembly. By removing the via patterning step entirely and using direct planar contact between first and second metallization layers, the invention solves the contradiction by achieving electrical connection without the complex via fabrication process
Solution Approach 2:
Instead of using vertical via structures to connect layers, the invention inverts the approach by using horizontal planar contact surfaces. The first metallization layer is formed as a planar surface that directly contacts the second metallization layer, eliminating the need for vertical via connections
2Object-affected harmful factors
If decoupling capacitance is increased to reduce power supply noise, then power delivery network performance improves, but chip area increases
Solution Approach 1:
The patent merges the decoupling capacitance function directly into the backside metallization power delivery network structure. By forming first and second metallization layers with planar contact on the substrate backside, the invention creates inherent decoupling capacitance without requiring separate capacitor structures, thus reducing power supply noise without proportionally increasing chip area
Solution Approach 2:
The invention moves the power delivery network and decoupling capacitance formation to the substrate backside dimension. By forming metallization layers on the opposite side from the active circuitry, the invention utilizes the third dimension (substrate thickness) to accommodate power delivery structures without consuming additional planar chip area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances chip performance by increasing decoupling capacitance and reducing power supply noise while simplifying the fabrication process by eliminating the need for via patterning.
Implementation Method 1
This, in turn, can increase the decoupling capacitance while reducing power supply noise
Implementation Method 2
the dielectric barrier layer comprises a high-k dielectric material
Data Source
AI summary
A semiconductor structure includes a first metallization layer having a first plurality of metal containing lines, and a second metallization layer located above the first metallization layer. The second metallization layer includes a second plurality of metal containing lines. A first group of the second plurality of metal containing lines is disposed within the first metallization layer. The first group of the second plurality of metal containing lines is isolated from the first metallization layer by a dielectric barrier layer.