Backside MIM Capacitor Trenches for Dense Low-Impedance Power Rails
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Solution Overview
Problem
Deep trench capacitors used in semiconductor devices have a high aspect ratio and pitch that are not suitable for higher-density semiconductor devices, limiting their application in advanced transistor architectures such as nanosheet and FinFETs due to impedance and density constraints.
Innovation Solution
The formation of backside metal-insulator-metal (MIM) capacitors in trenches between backside power rails, using a dielectric layer and interlayer dielectric layer, with recesses filled with insulative material to create contacts, enabling lower-impedance power supply implementations with higher density and smaller pitch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If deep trench capacitors (DTCs) are used in eDRAM, then capacitor functionality is achieved, but the high aspect ratio (greater than 10:1) and large pitch (greater than 1 micron) make them unsuitable for higher-density semiconductor devices
Solution Approach 1:
The patent inverts the conventional capacitor formation approach by forming backside power rails (BPRs) on the backside of the wafer after BEOL layers are formed, rather than forming capacitors in the conventional front-side deep trench approach. This inversion allows for smaller pitch and improved density while maintaining capacitor functionality.
Solution Approach 2:
The patent moves the capacitor formation to another dimension by utilizing the backside of the wafer for power rail formation and extending trenches through multiple layers (BILD layer, semiconductor layer, and dielectric layer) to create capacitors with reduced aspect ratios compared to conventional front-side deep trench capacitors.
2Quantity of substance
If deep trench capacitors with depth greater than 10 microns are used, then capacitor capacity is achieved, but the large gate pitch (greater than 1 micron) limits applicability to higher-density devices with gate pitch less than 100 nm
Solution Approach 1:
The patent nests the capacitor structure within the existing multi-layer architecture by forming trenches that extend through the BILD layer, semiconductor layer, and dielectric layer, with metal layers and insulative materials nested within the trench to create compact capacitor structures that achieve required capacity with reduced pitch.
Solution Approach 2:
The patent changes critical parameters by reducing the gate pitch from greater than 1 micron to less than 100 nm, and reducing the aspect ratio from greater than 10:1 to smaller values, while maintaining capacitor capacity through the backside power rail configuration and multi-layer trench structure.
Data Source
AI summary
A method of fabricating a semiconductor device comprises forming backside power rails in a dielectric layer arranged above a backside interlayer dielectric (BILD) layer or a semiconductor layer, forming a trench that extends through the BILD layer or the semiconductor layer and partly through the dielectric layer between the backside power rails, depositing a plurality of layers to form a backside metal-insulator-metal (MIM) capacitor in the trench, and forming a first contact to a first metal layer of the plurality of layers. Forming the first contact comprises forming first recesses in a second metal layer of the plurality of layers, and filling the first recesses with an insulative material. The method further comprises forming a second contact to the second metal layer. Forming the second contact comprises forming second recesses in the first metal layer, and filling the second recesses with the insulative material.