Backside MIM Capacitors With High-k Dielectrics for Dense Power Decoupling
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Solution Overview
Problem
As semiconductor devices continue to integrate more components into a given area through reduced minimum feature sizes, challenges arise in stabilizing power supply and electrical ground lines, necessitating improved decoupling capacitors that can hold greater charges while minimizing size.
Innovation Solution
Formation of metal-insulator-metal (MIM) capacitors in the back-end-of-the-line (BEOL) process on the backside of semiconductor dies, utilizing high-k dielectric materials to stabilize power supply and electrical ground lines, and forming MIM capacitors by removing portions of dielectric layers between conductive lines and lining sidewalls with high-k dielectric material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If decoupling capacitors are made larger to hold greater charges, then charge holding capacity is improved, but device area is increased
Solution Approach 1:
The patent employs metal-insulator-metal (MIM) capacitor structure with high-k dielectric materials to achieve higher charge holding capacity in a reduced area. The composite structure uses multiple metal layers separated by a high-k insulator, which provides higher capacitance density compared to conventional capacitors, thereby resolving the contradiction between charge capacity and area occupation.
Solution Approach 2:
The patent changes the dielectric constant parameter by using high-k dielectric materials instead of conventional low-k materials. This parameter change enables the capacitor to store more charge per unit area, directly addressing the technical contradiction by improving charge holding capacity without proportionally increasing the device area.
2Productivity
If minimum feature size is reduced to increase integration density, then integration density is improved, but manufacturing precision requirements are increased
Solution Approach 1:
The patent moves the decoupling capacitors to the backside of the semiconductor die, utilizing the vertical dimension and backside space that would otherwise be unused. This dimensional relocation allows integration of capacitor structures without occupying additional planar area on the front side, thereby improving integration density without imposing stringent precision requirements on minimum feature sizes.
Solution Approach 2:
The MIM capacitor structure is nested within the existing interconnect layers and conductive lines on the backside of the die. The capacitor formation is integrated into the existing BEOL process flow, with conductive lines and dielectric layers forming the capacitor structure in a nested manner, achieving high integration density without requiring separate manufacturing steps that would increase precision requirements.
3Quantity of substance
If MIM capacitors are formed by removing dielectric layers and lining sidewalls, then charge holding capacity is improved, but device complexity is increased
Solution Approach 1:
The patent merges the capacitor formation process with the existing interconnect fabrication process. The same dielectric layers and conductive lines that form the interconnect structure are also used to form the capacitor structure. By combining these functions into a single integrated process, the charge holding capacity is improved without proportionally increasing device complexity, as the capacitor formation utilizes existing process steps rather than requiring entirely separate fabrication sequences.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The MIM capacitors enhance device performance by allowing for greater charge holding capacity while minimizing size, stabilizing power supply and electrical ground lines, and improving integration density.
Implementation Method 1
Metal-insulator-metal (MIM) capacitors... utilizing high-k dielectric materials to stabilize power supply and electrical ground lines
Implementation Method 2
utilizing high-k dielectric materials... forming MIM capacitors by removing portions of dielectric layers between conductive lines and lining sidewalls with high-k dielectric material
Data Source
AI summary
A method of forming a semiconductor device includes: forming a device layer that includes nanostructures and a gate structure around the nanostructures; forming a first interconnect structure on a front-side of the device layer; and forming a second interconnect structure on a backside of the device layer, which includes: forming a dielectric layer along the backside of the device layer using a first dielectric material; forming a first conductive feature and a second conductive feature in the dielectric layer; form an opening in the dielectric layer between the first and the second conductive features; forming a first barrier layer and a second barrier layer along a first sidewall of the first conductive feature and along a second sidewall of the second conductive feature, respectively; and forming a second dielectric material different from the first dielectric material in the opening between the first barrier layer and the second barrier layer.