Backside-Interconnect MMIC Packaging for Lower EM Coupling

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Solution Overview

Problem

The increasing miniaturization of RF integrated circuits, particularly MMICs, leads to unwanted electromagnetic coupling with nearby metal features in packaging, affecting performance, especially at frequencies above 2 GHz, due to fanout-style packaging techniques like FOWLP and FOPLP.

Innovation Solution

Implementing backside interconnects, also known as hot vias, in MMICs to orient the chip side away from the redistribution layer (RDL) and using an overmold layer for improved thermal paths, which reduces electromagnetic interference and enhances heat dissipation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If fanout-style packaging is used to achieve high-density packaging, then packaging density is improved, but electromagnetic coupling between MMIC die and metal features in RDL increases

Engineering Contradiction:

Improvepackaging densityVSAvoidelectromagnetic coupling

Core Design Contradiction:

Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

The patent inverts the conventional packaging approach by using backside interconnects instead of front-side interconnects. The MMIC die is packaged with interconnects on the backside, allowing the front side to be oriented away from the RDL metal features, thereby reducing electromagnetic coupling while maintaining high-density packaging benefits

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The patent transitions from planar front-side interconnection to three-dimensional backside interconnection. By moving the interconnect interface to the backside of the die and utilizing vertical stacking with RDL layers, the design achieves high-density packaging in the vertical dimension while separating the RF-sensitive front side from interfering metal features

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If chip side is oriented toward RDL for conventional packaging, then electrical connection is simplified, but electromagnetic interference increases

Engineering Contradiction:

Improveelectrical connectionVSAvoidelectromagnetic interference

Core Design Contradiction:

Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The patent inverts the conventional orientation by placing the interconnect interface on the backside of the die rather than the front side. This allows the front side with RF components to be oriented away from the RDL, reducing electromagnetic interference while the backside handles all electrical connections to the package substrate

Inventive Principle:

Principle #13The other way round (Inversion)

3Object-affected harmful factors

If backside interconnects are used to reduce electromagnetic coupling, then electromagnetic interference is reduced, but thermal dissipation path is altered

Engineering Contradiction:

Improveelectromagnetic interferenceVSAvoidthermal dissipation

Core Design Contradiction:

Object-affected harmful factorsVSTemperature

Solution Approach 1:

The patent introduces the overmold layer as an intermediary thermal management component. The overmold layer with its thermally conductive material provides an alternative thermal dissipation path from the die, compensating for the altered thermal path caused by backside interconnect packaging, while simultaneously providing mechanical protection and electrical isolation

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration minimizes electromagnetic coupling, improves thermal conductivity, and maintains high-density packaging, effectively shielding RF circuits from interference and optimizing performance in high-frequency environments.

Implementation Method 1

This can also facilitate improved thermal paths for heat dissipation, such as through the RDL or through an overmold layer of the circuit package

Methodology Applied

Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

fanout-style packaging may produce undesired electromagnetic (EM) coupling between a MMIC die and metal features in a redistribution layer (RDL) of the FOW/PLP package

Methodology Applied

Scientific EffectElectromagnetic coupling: Electromagnetic Induction

Data Source

PatentUS11791312B2MMICs with backside interconnects for fanout-style packaging

Publication Date: 2023.10.17 QORVO US INC

AI summary

Monolithic microwave integrated circuits (MMICs) with backside interconnects for fanout-style packaging are disclosed. Fanout-style packaging, such as fanout wafer (FOWLP) or fanout panel-level packaging (FOPLP), facilitates a high density package for MMICs. However, the fanout-style packaging may produce undesired electromagnetic (EM) coupling between a MMIC die and metal features in a redistribution layer (RDL) of the FOW/PLP package and/or a next higher assembly (NHA). In an exemplary aspect, a circuit package according to this disclosure includes the MMIC die and an RDL. The MMIC includes a chip side with components which may undesirably couple to metal signal lines (e.g., package metal interconnects) in the RDL. The chip side of the MMIC is oriented away from the RDL to reduce such EM coupling.