Backside Molding Layer Protects TSV Electrodes in Stack Packages

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Solution Overview

Problem

The challenge in semiconductor device manufacturing is to reduce the thickness and size of stack packages while ensuring the integrity of through silicon via (TSV) electrodes, which are prone to damage and peeling issues due to the existing packaging methods, leading to potential package failures.

Innovation Solution

The implementation of a backside molding layer made of epoxy molding compound (EMC) that covers and protects the backside end portions of TSV electrodes, preventing damage during grinding and ensuring the package molding layer adheres properly, thereby preventing peeling and maintaining the structural integrity of the semiconductor device.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If the thickness and size of stack packages are reduced, then the miniaturization and integration of semiconductor devices are improved, but the TSV electrodes become more prone to damage and peeling issues

Engineering Contradiction:
Improvepackage sizeVSAvoidTSV electrode integrity
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

A backside molding layer is formed to cover the backside surface of the semiconductor substrate before packaging. This molding layer acts as a protective cushion that prevents damage to the TSV electrodes during the packaging process and reduces peeling issues by providing mechanical support to the vulnerable TSV structures in miniaturized packages.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Ease of manufacture

If conventional packaging methods are used without backside protection, then the manufacturing process is simpler, but the TSV electrodes suffer from damage and peeling leading to package failures

Engineering Contradiction:
Improvepackaging process simplicityVSAvoidpackage failure rate
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The backside molding layer is formed in advance during the substrate processing stage, before the chips are mounted and packaged. This preliminary action protects the TSV electrodes from the beginning, preventing damage during subsequent handling and packaging operations without complicating the overall manufacturing flow.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If the TSV electrodes are made longer to penetrate through the substrate, then the electrical connection is improved, but the electrodes become more vulnerable to damage during packaging

Engineering Contradiction:
Improveelectrical connection integrityVSAvoidTSV electrode damage susceptibility
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The backside molding layer provides protective cushioning around the TSV electrodes that extend through the substrate. This cushioning effect prevents mechanical damage to the long electrodes during packaging operations while maintaining their electrical connection function, effectively resolving the vulnerability issue associated with longer penetrating electrodes.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS9117938B2Semiconductor devices with through via electrodes, methods of fabricating the same, memory cards including the same, and electronic systems including the same
Publication Date: 2015.08.25 SK HYNIX INC
  • US9117938B2 patent drawing
  • US9117938B2 patent drawing
  • US9117938B2 patent drawing

AI summary

A semiconductor device includes a via electrode penetrating a substrate and a back-side molding layer covering a back-side surface of the substrate. The back-side molding layer contacts a sidewall of a back-side end portion of the via electrode, which is a portion of the via electrode that protrudes from the back-side surface of the substrate.