Backside MRAM Integration with Self-Aligned Micro Studs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional MRAM placement on the frontside of wafers leads to routing congestion and limits the stability and performance of MRAM due to the proximity of word lines, source lines, and bit lines, making it difficult to achieve efficient integration with transistors.
Innovation Solution
The integration of a relaxed pitch backside magneto-resistive random access memory (MRAM) with a self-aligned micro stud and backside power distribution network, allowing direct contact between MRAM and transistor source/drain, and relocating the bit line to the backside of the wafer to alleviate congestion and improve MRAM performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If MRAM is placed on the frontside of the wafer, then integration with transistor is achieved, but routing congestion occurs and MRAM stability deteriorates due to proximity of word lines, source lines, and bit lines
Solution Approach 1:
The patent moves MRAM from the frontside to the backside of the wafer, utilizing the third dimension (depth/layer) to resolve the contradiction. This dimensional transition separates MRAM from the congested frontside routing environment while maintaining integration capability through backside contact to transistor source/drain regions, thereby improving both reliability and reducing routing congestion.
Solution Approach 2:
The patent segments the wafer into frontside and backside regions, placing different functional blocks on opposite sides. Logic circuits remain on the frontside while MRAM is placed on the backside, allowing independent optimization of each region without mutual interference from routing congestion.
2Ease of manufacture
If MRAM is placed on the frontside of the wafer, then integration with transistor is achieved, but routing congestion occurs
Solution Approach 1:
By relocating MRAM to the backside of the wafer, the patent eliminates routing congestion on the frontside. The bit line can be directly contacted from the backside to the transistor source/drain regions, simplifying the routing architecture and reducing overall device complexity while maintaining integration.
3Ease of manufacture
If conventional front side MRAM placement is used, then integration is achieved, but MRAM performance is limited due to routing congestion
Solution Approach 1:
The backside placement of MRAM enables superior performance by eliminating routing congestion that limits frontside implementations. The direct backside contact to transistor source/drain regions provides lower resistance paths and reduced signal interference, thereby improving MRAM operational performance and speed.
Data Source
AI summary
A semiconductor device includes a magneto-resistive random access memory (MRAM) formed at a backside of a wafer. A self-aligning micro stud and silicide layer can directly electrically connect the MRAM to a source/drain (S/D) of a transistor in the MRAM region of the semiconductor device.