Backside N-Type Layer Design for Snap-Off Suppression
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Solution Overview
Problem
Conventional pin diodes face issues with snap-off and oscillation phenomena during turn-off operations, leading to breakdowns due to high carrier concentration and parasitic pnp bipolar transistor structures, which deteriorate avalanche resistance.
Innovation Solution
A semiconductor device design where an n-type layer is formed on the rear surface of the n-type buffer layer in the boundary region between the active and terminal regions, with an extending distance of 10 μm to 500 μm, suppressing snap-off and oscillation phenomena and improving avalanche resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If wafer thinning is applied to reduce forward voltage drop, then forward voltage drop is reduced, but tolerance of snap-off during recovery is reduced
Solution Approach 1:
The patent applies different doping concentrations and layer structures to different regions of the semiconductor device. Specifically, the drift layer has a first doping concentration in the active region and a second doping concentration in the terminal region, with the second being higher than the first. This local differentiation allows the active region to maintain low forward voltage drop while the terminal region provides enhanced snap-off tolerance.
Solution Approach 2:
The patent extends the solution from a single-layer structure to a multi-layer structure by introducing an intermediate layer between the drift layer and the cathode contact layer. This intermediate layer has a doping concentration that is higher than the drift layer but lower than the cathode contact layer, creating a gradual transition that resolves the contradiction between low forward voltage drop and snap-off tolerance.
2Reliability
If carrier concentration in terminal region is reduced to improve recovery SOA, then recovery SOA is improved, but carrier concentration on boundary region during recovery increases
Solution Approach 1:
The patent implements local quality by establishing distinct doping concentration zones: the terminal region has a higher doping concentration to reduce carrier concentration during recovery and improve recovery SOA, while the active region maintains lower doping concentration. The intermediate layer provides a controlled transition zone that prevents excessive carrier concentration buildup at the boundary during recovery operations.
3Loss of energy
If substrate concentration is increased and n- type drift layer thickness is reduced to reduce total loss, then total loss is reduced, but breakdown occurs simultaneously with avalanche exceeding rated voltage
Solution Approach 1:
The patent changes the doping concentration parameter across different layers to resolve the contradiction. By setting the drift layer doping concentration to a first value and the intermediate layer to a second value (higher than the first), the device achieves reduced total loss through optimized drift layer design while the intermediate layer prevents simultaneous breakdown with avalanche by providing a controlled electric field distribution.
4Reliability
If n type layer is formed on rear surface in boundary region, then snap-off and oscillation phenomena are suppressed, but device complexity increases
Solution Approach 1:
The patent resolves the contradiction by adding another dimensional layer (the intermediate layer) between the drift layer and cathode contact layer. This additional layer, with its specific doping concentration profile, suppresses snap-off and oscillation phenomena by controlling carrier distribution and electric field characteristics, while the systematic approach to layer design keeps the complexity manageable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively prevents breakdowns and enhances avalanche resistance during turn-off and off-operations by reducing electric field concentration and carrier depletion, maintaining RFC effects and improving surge voltage characteristics.
Implementation Method 1
reducing electric field concentration and carrier depletion
Implementation Method 2
improving avalanche resistance
Data Source
AI summary
A p type anode layer is formed on a front surface of an n type drift layer in an active region. An n type buffer layer is formed on a rear surface of the n− type drift layer. An n type cathode layer and a p type cathode layer are formed side by side on a rear surface of the n type buffer layer. An n type layer is formed on the rear surface of the n type buffer layer in a boundary region between the active region and the terminal region side by side with the n type cathode layer and the p type cathode layer. An extending distance of the n type layer to the active region side with an end portion of the active region as a starting point is represented by WGR1, and WGR1 satisfies 10 μm≤WGR1≤500 μm.