Backside Optical Routing Structure for High-Temperature Photonic Integration
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Solution Overview
Problem
The formation of silicon nitride optical routing structures in photonic devices is limited by high-temperature annealing processes, which can damage other features in the circuit, leading to inefficient and large package structures due to structural and manufacturing limitations.
Innovation Solution
The integration of photonic devices with upper optical routing structures on the frontside and lower optical routing structures on the backside of a silicon-on-insulator (SOI) substrate, utilizing silicon nitride on the backside to optimize photon travel and reduce package size, with anti-reflective and reflective layers and micro-lenses to enhance optical communication and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature annealing processes are used to form silicon nitride optical routing structures, then optical routing functionality is achieved, but other features in the circuit are damaged
Solution Approach 1:
The patent forms optical routing structures on the backside of the substrate rather than on the frontside where sensitive circuit features are located. This spatial separation in the vertical dimension allows high-temperature annealing to be performed without exposing the frontside circuit features to thermal damage, thus resolving the contradiction between achieving optical routing functionality and protecting other circuit features.
2Reliability
If traditional frontside optical routing structures are used, then optical communication is achieved, but package size increases
Solution Approach 1:
By moving the optical routing structures to the backside of the substrate, the patent utilizes the vertical dimension more effectively. This allows the frontside to be dedicated to circuit features while the backside handles optical routing, enabling more compact integration and reducing overall package size while maintaining optical communication functionality.
Solution Approach 2:
The patent separates the substrate into two functional zones: the frontside for circuit features and the backside for optical routing structures. This segmentation allows each side to be optimized independently, with the backside optical routing structures enabling more efficient space utilization and smaller package size.
3Ease of manufacture
If silicon nitride is used for optical routing on the frontside, then manufacturing is simplified, but high-temperature processing damages other features
Solution Approach 1:
The patent forms silicon nitride optical routing structures on the backside of the substrate, allowing the full benefits of silicon nitride fabrication (simplified manufacturing process, good optical properties) to be realized without exposing the frontside circuit features to the high-temperature annealing required for silicon nitride formation. This resolves the contradiction between ease of manufacture and circuit feature integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases device reliability and efficiency, reduces package size, and allows for high-temperature processing of silicon nitride without damaging frontside features, improving optical communication and device density.
Implementation Method 1
an anti-reflective layer arranged below and directly contacting the substrate
Implementation Method 2
a micro-lens arranged between the lower optical routing structure and a topmost surface of the substrate
Implementation Method 3
utilizing silicon nitride on the backside to optimize photon travel
Data Source
AI summary
In some embodiments, the present disclosure relates to an integrated chip that includes an insulator layer arranged over a substrate. Further, an upper routing structure is arranged over the insulator layer and is made of a semiconductor material. A lower optical routing structure is arranged below the substrate and is embedded in a lower dielectric structure. The integrated chip further includes an anti-reflective layer that is arranged below the substrate and directly contacts the substrate.