Backside Output Circuit Layout for High-Current Compact ICs
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Solution Overview
Problem
Existing semiconductor integrated circuit devices face challenges in designing an output circuit that can pass a large current without requiring an expanded layout area, particularly when transistors are stacked and interconnects are positioned beneath them.
Innovation Solution
The output circuit is designed with first and second active regions of a transistor overlapping in planar view, and power and output lines are placed on the backside of the transistor, connected through vias, allowing for a compact layout that can handle high current without enlarging the circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistors are stacked one upon another with interconnects laid right under the transistors, then integration density is improved, but current passing capability of output circuit deteriorates
Solution Approach 1:
The patent utilizes the vertical dimension by stacking transistors one upon another, with interconnects positioned in the space beneath the transistor structures. This three-dimensional arrangement allows multiple transistor layers to share common interconnect layers, significantly improving integration density while maintaining adequate current passing capability through proper via connections to source and drain regions.
Solution Approach 2:
The output circuit is divided into multiple transistor layers (first transistor layer, second transistor layer, etc.), each with its own active regions, gates, and interconnects. This segmentation allows the current path to be distributed across multiple layers, with each layer contributing to the overall current passing capability while maintaining compact footprint.
2Area of stationary object
If layout area is reduced for compact design, then integration is improved, but current passing capability deteriorates
Solution Approach 1:
By transitioning from planar to vertical stacking, the patent achieves high integration density without proportionally reducing current passing capability. The vertical arrangement allows multiple transistor layers to occupy the same footprint area while providing separate current paths through via connections to source and drain regions.
Solution Approach 2:
Multiple transistor layers are nested vertically within the same footprint area, with each layer containing complete transistor structures (source, drain, gate). The interconnects are nested in the space beneath the transistor layers, creating a compact three-dimensional structure that maintains adequate current passing capability.
Data Source
AI summary
In an output circuit of a semiconductor integrated circuit device, an output transistor part including a transistor connected between VSS and an output terminal has first and second active regions overlapping each other in planar view. A power line and an output line are placed in an interconnect layer on the back side so as to overlap the first and second active regions in planar view. The power line is connected to the lower face of the portion that is to be the source of the first active region through a via, and the output line is connected to the lower face of the portion that is to be the drain of the first active region through a via.