Backside Oxide Barrier for Body Biasing Attack Protection

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Solution Overview

Problem

Integrated circuits, particularly those with wafer-level chip-scale packaging, are vulnerable to body biasing injection (BBI) attacks due to the exposure of the back side of the die, which can be exploited to inject voltage glitches and compromise security assets like the root of trust and die-to-die interconnects, with current defenses being non-existent.

Innovation Solution

Implementing an oxide layer (1-2 um thick) on the back side of stacked silicon dies, combined with a permanently attached carrier, such as a glass or silicon carrier with thermal vias, to provide electrical insulation and thermal conductivity, preventing voltage glitches from reaching the power subsystem and securing security assets.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the back side of the die is exposed (wafer-level chip-scale packaging), then packaging efficiency and integration are improved, but vulnerability to body biasing injection attacks increases

Engineering Contradiction:
Improvepackaging efficiencyVSAvoidvulnerability to BBI attacks
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

An oxide layer is introduced as an intermediary barrier between the exposed back side of the die and the power subsystem. This oxide layer physically blocks voltage glitches from propagating through the bulk silicon to sensitive circuits, while allowing the packaging structure to remain exposed for thermal management purposes.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

A thin oxide film is deposited on the back side of the die to provide electrical insulation and protect against BBI attacks. The thin film structure maintains the overall exposed configuration of the packaging while providing the necessary security barrier.

Inventive Principle:
Principle #30Flexible shells and thin films

2Reliability

If an oxide layer is added on the back side of the die, then protection against voltage glitches is improved, but device complexity increases

Engineering Contradiction:
Improveprotection against voltage glitchesVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The oxide layer parameters (thickness, material composition) are optimized to provide effective electrical insulation against voltage glitches while maintaining compatibility with existing manufacturing processes. The thickness is controlled to be sufficient for protection but thin enough to avoid excessive complexity.

Inventive Principle:
Principle #35Parameter changes

3Temperature

If thermal vias are implemented in the carrier, then thermal conductivity is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvethermal conductivityVSAvoidmanufacturing complexity
Core Design Contradiction:
TemperatureVSEase of manufacture

Solution Approach 1:

The carrier is segmented with thermal vias that create localized thermal conduction paths. These vias are strategically positioned to provide thermal management where needed while leaving other areas of the carrier simple and easy to manufacture.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Thermal via holes are created only in specific locations where thermal conduction is required, rather than throughout the entire carrier. This localized approach provides thermal management functionality while minimizing the increase in manufacturing complexity.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The oxide layer and carrier combination effectively blocks voltage glitches, protecting security assets from BBI attacks while maintaining thermal conductivity, suitable for applications without a heat sink, such as internet of things devices.

Implementation Method 1

the oxide layer restricts voltage glitches from reaching a power subsystem of the stacked silicon die

Methodology Applied
Scientific EffectElectrical insulation: Dielectric

Implementation Method 2

a permanently attached carrier (e.g., silicon carrier, glass carrier, etc.)... providing sufficient thermal conductivity

Methodology Applied
Scientific EffectThermal conductivity: Conduction (thermal)

Data Source

PatentUS20250343039A1Systems and methods for preventing body biasing injection attacks
Publication Date: 2025.11.06 ADVANCED MICRO DEVICES INC
  • US20250343039A1 patent drawing
  • US20250343039A1 patent drawing
  • US20250343039A1 patent drawing

AI summary

A computer-implemented method for preventing body biasing attacks can include providing a stacked silicon die. The method can also include providing an oxide layer on a back side of the stacked silicon die, wherein the oxide layer restricts voltage glitches from reaching a power subsystem of the stacked silicon die. The method can further include permanently attaching a carrier to the oxide layer. Various other methods, systems, and computer-readable media are also disclosed.