Backside Package Architecture for HBM Power and Signal Routing
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Solution Overview
Problem
Existing microelectronics packaging technologies face challenges in efficiently connecting and integrating multiple computational components across different substrates, particularly in forming effective backside power networks that support high bandwidth memory modules.
Innovation Solution
The proposed solution involves a package architecture that integrates a backside power delivery network (BSPDN), a signal network, and high bandwidth memory modules. This architecture includes a transistor layer separating the signal network from the BSPDN, with the BSPDN formed on the backside of a substrate and the signal network on the front side, enabling efficient power delivery and signal routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If connections are formed between substrates to integrate multiple computational components, then computation capability is increased, but packaging complexity and connection difficulty increase
Solution Approach 1:
The package substrate is divided into distinct functional layers: a first substrate layer containing power delivery network traces, a second substrate layer containing signal network traces, and intermediate bonding layers. This segmentation allows independent optimization of power and signal paths while simplifying the overall integration process
Solution Approach 2:
The patent transitions from planar 2D routing to 3D stacked architecture by forming connections between front and back sides of substrates. Through-holes and vias enable vertical interconnections, allowing power and signal networks to operate in different spatial dimensions simultaneously, thereby increasing computation capability without proportionally increasing packaging complexity
2Use of energy by moving object
If backside power networks are formed to support high bandwidth memory modules, then power delivery efficiency is improved, but manufacturing difficulty increases
Solution Approach 1:
Power delivery network traces are formed on the first substrate layer before bonding to the second substrate layer. This preliminary formation of power networks allows for optimized trace routing and impedance control before the complex stacking process, reducing manufacturing difficulty while maintaining high power delivery efficiency
Solution Approach 2:
Conductive bonding layers and intermediate substrates serve as mediators between the power delivery network on the first substrate and the memory modules. These intermediary elements facilitate controlled impedance matching and simplify the bonding process, reducing manufacturing complexity while enabling efficient power delivery to high bandwidth memory
3Productivity
If signal networks are routed between transistor layer and memory module, then signal routing capability is improved, but routing congestion increases
Solution Approach 1:
Signal networks are routed on the second substrate layer, which is positioned vertically above the transistor layer. This vertical stacking approach allows signal routing in a different spatial dimension, increasing signal routing capability while minimizing congestion on the transistor layer by separating signal and power routing paths in 3D space
Data Source
AI summary
A method, system, and device are disclosed herein where a first layer includes at least one transistor, a second layer on a first side of the first layer includes a signal network, a third layer on a second side of the first layer, opposite the first side, includes a backside power delivery network, and a memory module is coupled to the signal network. The backside power delivery network, the at least one transistor, and the signal network may provide a logic circuit for the memory module.