Backside Pad-Via Routing for Dense 3D Memory Interconnects
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Solution Overview
Problem
Conventional semiconductor device connections result in increased separation distances, structural instability, and higher resistance due to the use of interconnects and vias, which hinder the ability to achieve higher signal density and efficient 3D routing without affecting the front-side circuit layout.
Innovation Solution
Implementing a backside (BS) connection mechanism using a dual damascene (DD) manufacturing process to form integral, continuous traces and vias, allowing for lateral and vertical signal routing without affecting the front-side circuit layout, thereby reducing thickness and resistance while providing additional structural support.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional interconnects and vias are used for connections, then electrical connectivity is achieved, but separation distance increases and resistance increases
Solution Approach 1:
The patent transitions from conventional planar interconnects to three-dimensional vertically-aligned conductive structures (via holes filled with conductive material) that extend through the substrate thickness. This vertical routing in the Z-dimension reduces the lateral separation distance between connection points while maintaining electrical connectivity, directly resolving the contradiction between connection stability and separation distance.
2Reliability
If conventional interconnects and vias are used for connections, then electrical connectivity is achieved, but resistance increases
Solution Approach 1:
The patent employs composite conductive structures consisting of multiple material layers including conductive fillers (such as copper or other low-resistance materials) within the via holes, potentially combined with conductive polymers or metallic coatings. This composite approach reduces the overall resistance of the vertical interconnects while maintaining structural integrity and connection stability.
3Productivity
If front-side circuit layout is modified to achieve higher signal density, then signal density improves, but existing circuit functionality is affected
Solution Approach 1:
The patent implements vertical routing through the substrate thickness using via holes and conductive structures in the Z-dimension, allowing signal density to be increased without modifying the lateral (X-Y plane) circuit layout. This dimensional transition enables higher signal density while preserving the functionality of existing front-side circuits.
4Productivity
If device thickness is reduced to improve integration, then manufacturing efficiency improves, but structural integrity deteriorates
Solution Approach 1:
The patent uses composite material structures including substrate materials combined with embedded conductive layers, dielectric materials, and reinforcement structures that provide mechanical strength. These composite constructions maintain structural integrity even when the overall device thickness is reduced for improved manufacturing efficiency and integration.
Data Source
AI summary
Methods, apparatuses, and systems related to a memory device having on its backside one or more integrally-formed structures is described. A memory device may include a backside pad-via structure, a backside redistribution layer structure, or a combination thereof. Such backside structures may include integrally-formed portions that extend in different directions to laterally route electrical signals on the backside.