Backside Passivation Layer for Threshold-Stable Power Delivery
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Solution Overview
Problem
Backside power delivery in semiconductor devices often introduces threshold voltage shifts due to trap charges introduced during the etching process, which is undesirable for transistor performance and layout consistency.
Innovation Solution
A passivation layer, such as a 5 nm silicon nitride layer, is applied after backside etching, followed by an ozone/ultraviolet light treatment to remove trap charges, thereby mitigating or eliminating threshold voltage shifts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If backside power delivery is implemented, then resistance path is reduced and space is opened on frontside, but threshold voltage shift is introduced
Solution Approach 1:
A passivation layer is introduced as an intermediary between the etching process and the transistor semiconductor material. This layer prevents direct interaction between the etch chemistry and the transistor structure, thereby eliminating threshold voltage shift while allowing backside power delivery to proceed
Solution Approach 2:
The passivation layer is applied before the etching process to preemptively protect the transistor semiconductor material from threshold voltage shift. This preliminary protective action prevents the harmful effect from occurring in the first place, rather than attempting to correct it afterward
2Ease of operation
If backside etching is performed to enable power delivery, then access to backside is achieved, but trap charges are introduced causing threshold voltage shift
Solution Approach 1:
The passivation layer serves as a protective intermediary that allows the etching process to access the backside while preventing the generation of trap charges in the transistor semiconductor material. The layer is selectively removed only where needed for power delivery
3Reliability
If passivation layer is applied after backside etch, then threshold voltage shift is reduced, but additional process step is added
Solution Approach 1:
The passivation layer is applied as a preliminary step before etching, which actually simplifies the overall process by preventing the need for complex trap charge removal treatments afterward. The preliminary protection eliminates the need for ozone/UV annealing or other corrective processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces threshold voltage shifts by 15 to 20 mV, improving transistor performance and layout consistency by removing trap charges introduced during the backside etching process.
Implementation Method 1
performing an ozone and ultraviolet anneal of the first insulative layer
Implementation Method 2
performing an ozone and ultraviolet anneal of the first insulative layer
Data Source
AI summary
Devices, transistor structures, systems, and techniques are described herein related to providing a backside passivation layer on a transistor semiconductor material. The semiconductor material is between source and drain structures, and a gate structure is adjacent a channel region of the semiconductor material. The passivation layer is formed as a conformal insulative layer on a backside of the semiconductor material and is then treated using an ozone/UV cure to remove trap charges from the semiconductor material.