Backside Passive Device Integration on Semiconductor Dies
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Solution Overview
Problem
Conventional methods for reducing circuit board space in electronic devices, such as LTCC technology and flip chip technology, either increase manufacturing costs or require significant development effort without providing sufficient benefits.
Innovation Solution
Integrating passive devices like inductors and capacitors on the backside surface of semiconductor dies using thick copper deposition and semiconductor processes, allowing for finer spacing and higher quality factor inductors, and reducing the need for wirebonds by using through-wafer vias for connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If LTCC technology is used to embed passive devices in a ceramic substrate, then circuit board space is saved, but manufacturing cost increases
Solution Approach 1:
The patent utilizes the backside surface of the semiconductor die (a different spatial dimension) to integrate passive devices, thereby saving circuit board space without requiring expensive LTCC ceramic substrates. This dimensional approach allows passive devices to be formed directly on the die backside using standard semiconductor processes.
Solution Approach 2:
The patent combines active semiconductor devices and passive devices into a single integrated structure on the same die substrate. By merging these previously separate components into one unified device, the patent eliminates the need for external passive components and expensive LTCC packaging while reducing overall device footprint.
2Area of stationary object
If flip chip technology is used to surface mount a semiconductor die, then circuit board space is saved by eliminating wirebonds, but significant development effort and risk are required
Solution Approach 1:
The patent segments the die into two functional surfaces: the front side for active devices and the backside for passive devices. This segmentation allows each surface to be optimized independently using standard wirebond or flip-chip techniques, avoiding the complexity of reconfiguring the entire die while still achieving space savings.
3Ease of manufacture
If passive devices are formed using laminate-based technologies, then manufacturing is simpler, but inductor quality factor and inductance are lower
Solution Approach 1:
The patent changes the material parameters by using thick copper deposition (different from standard thin copper) and semiconductor-grade dielectric materials instead of laminate materials. These parameter changes enable the formation of high-Q inductors with superior electrical properties while maintaining compatibility with standard semiconductor manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach saves space on circuit boards, reduces manufacturing costs, and enhances the performance of passive devices by forming them using semiconductor processes, achieving higher inductance and quality factor compared to conventional laminate-based technologies.
Implementation Method 1
Integrating passive devices like inductors and capacitors on the backside surface of semiconductor dies using thick copper deposition
Data Source
AI summary
According to an exemplary embodiment, a semiconductor die includes a backside surface opposite an active surface. The active surface includes at least one active device. The semiconductor die includes at least one passive device situated on the backside surface. The semiconductor die further includes an interconnect region situated over the active surface. The semiconductor die further includes at least one through-wafer via, where the at least one through-wafer via electrically connects the at least one passive device to the interconnect region. The interconnect region can include a number of solder bump pads or a number of bond pads.