Backside Capacitor and Inductor Integration for Dense Low-Noise Chips
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Solution Overview
Problem
Current semiconductor chip designs face challenges with high-density integration of capacitors and inductors due to their large footprint in back-end-of-line (BEOL) wiring, which limits integration density and increases noise in power and ground lines.
Innovation Solution
Integrating capacitors and inductors on the backside of the chip with the backside power delivery network (BSPDN), reducing their footprint without downsizing, and allowing placement on both frontside and backside to meet performance requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If capacitors and inductors are implemented as discrete off-chip components, then their performance is adequate, but the chip package cost increases and module size increases
Solution Approach 1:
The patent merges capacitors and inductors with the BEOL wiring structure by forming these passive components using the same metallization layers and interconnect structures that are already present in the back-end-of-line processing. This integration eliminates the need for separate off-chip components while maintaining electrical performance, thereby reducing module size and packaging cost.
Solution Approach 2:
The BEOL metallization layers are designed to serve dual purposes: providing interconnects between frontside integrated circuit components and forming passive components (capacitors and inductors). This multi-functionality allows the same structural elements to fulfill multiple circuit requirements, reducing the overall component count and module footprint.
2Area of stationary object
If on-chip capacitors are used, then chip package cost is reduced and module size is reduced, but noise in power and ground lines increases when placed closer to loads
Solution Approach 1:
The patent transitions the placement of passive components from the traditional planar BEOL wiring layer to the vertical backside of the chip. By forming capacitors and inductors on the backside using backside electrical contacts connected to source/drain regions, the design utilizes the third dimension (vertical space) to house passive components, allowing closer placement to power and ground lines without increasing lateral footprint or noise interference.
3Reliability
If inductors are fabricated as off-chip components, then circuit performance is maintained, but series resistance increases and integration density decreases
Solution Approach 1:
The patent combines inductor fabrication with the BEOL wiring structure by patterning inductor coils in the wiring metallization levels. This integration allows inductors to be formed as part of the existing interconnect structure, reducing series resistance through direct metal-to-metal connections and enabling high-density integration without compromising circuit performance.
4Productivity
If inductors are constructed as part of the frontside integrated circuit, then integration density is improved, but the BEOL wiring structure becomes more complex
Solution Approach 1:
The patent inverts the conventional approach by moving passive component fabrication from the frontside BEOL wiring structure to the backside of the chip. This reversal simplifies the frontside BEOL wiring complexity while maintaining high integration density, as the backside processing can be performed independently using backside electrical contacts and separate fabrication steps.
Data Source
AI summary
A semiconductor device a first device located on a frontside of a semiconductor substrate. The semiconductor device further includes an inductor located on a backside of the semiconductor substrate and integrated with a first backside metal (BSM) stack. The semiconductor device further includes a first electrical contact located between the frontside and the backside of the semiconductor substrate. A first end of the first electrical contact is connected to the first BSM stack and a second end of the first electrical contact is connected to a first source/drain region of the first device.