Multi-Tier Backside PDN Layout for Dense 3D Logic Stacks
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Solution Overview
Problem
Conventional two-dimensional semiconductor fabrication faces challenges in scaling as it reaches single-digit nanometer nodes, necessitating a transition to three-dimensional integration to increase transistor density and integrate logic and memory circuits efficiently, while effectively addressing power delivery across multiple functional tiers remains a significant hurdle.
Innovation Solution
A multi-tier semiconductor structure is developed, featuring a power delivery network (PDN) with through-silicon vias (TSVs) and vertically stacked semiconductor device tiers, enabling efficient power and signal connectivity through multiple wiring levels and substrate-based power rails, allowing for dense integration of CMOS logic and memory in a compact, 3D format.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional scaling is continued to increase transistor density, then more transistors can be integrated on the substrate, but fabrication challenges increase significantly at single-digit nanometer nodes
Solution Approach 1:
The patent transitions from two-dimensional circuit layout to three-dimensional integration by stacking multiple functional tiers vertically. The substrate is organized into distinct tiers including first and second logic tiers, memory tiers, and interconnect tiers, connected through through-silicon vias. This vertical stacking enables continued transistor density scaling while avoiding the fabrication challenges of single-digit nanometer 2D scaling.
2Quantity of substance
If three-dimensional integration is implemented to increase transistor density, then scaling challenges are addressed, but power delivery across multiple functional tiers becomes significantly more complex
Solution Approach 1:
The power delivery network is segmented into tier-specific power delivery structures, with each functional tier (logic tiers, memory tiers) having its own dedicated power delivery network. This segmentation allows independent optimization of power delivery for each tier, reducing the overall complexity compared to a monolithic power distribution system.
Solution Approach 2:
Through-silicon via structures serve as intermediary elements that penetrate the substrate to provide vertical electrical connectivity between different tiers. These TSVs act as mediators for power and signal transmission across the three-dimensional structure, enabling efficient power delivery to stacked functional blocks without requiring complex lateral routing.
3Productivity
If vertical stacking of logic and memory cells is implemented, then wire-length is reduced and integration density is improved, but power delivery network structure becomes more complex
Solution Approach 1:
The patent implements vertical stacking of logic and memory cells across multiple tiers connected by through-silicon vias, reducing lateral wire-length and improving integration efficiency. The three-dimensional arrangement places frequently interacting logic and memory blocks in close vertical proximity, minimizing interconnect length while maintaining functional separation.
Solution Approach 2:
The power delivery network is segmented into tier-specific structures, with each stacked functional block having its own localized power delivery network. This segmentation reduces the complexity of the overall power delivery system by breaking it into manageable, independent modules that can be designed and optimized separately.
Data Source
AI summary
Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the multi-tier semiconductor structure can include a first power delivery network (PDN) structure, and a first semiconductor device tier disposed over and electrically connected to the first PDN structure. The multi-tier semiconductor structure can further include a signal wiring tier disposed over and electrically connected to the first semiconductor device tier, a second semiconductor device tier disposed over and electrically connected to the signal wiring tier, and a second PDN structure disposed over and electrically connected to the second semiconductor device tier. The multi-tier semiconductor structure can further include a through-silicon via (TSV) structure electrically connected to the signal wiring tier, wherein the TSV structure penetrates the second PDN structure.