Backside Photodiode Layout for Isolated High-Voltage Routing
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Solution Overview
Problem
Existing backside illumination (BSI) single photon avalanche diode (SPAD) image sensors face challenges in circuit design and manufacturing due to high-voltage routings that traverse through both the sensor die and the application-specific integrated circuit (ASIC) die, leading to dielectric breakdown and signal interference issues.
Innovation Solution
The proposed solution involves bonding a sensor die to an ASIC die with high-voltage interconnect structures contained within the sensor die, allowing the high-voltage routings to remain within the sensor die while the ASIC die is free of high-voltage operations, thereby reducing manufacturing complexity and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-voltage routings traverse through both sensor die and ASIC die, then electrical connection is achieved, but dielectric breakdown and signal interference occur
Solution Approach 1:
The patent segments the high-voltage routing path by confining it entirely within the sensor die. The sensor die contains high-voltage power supply circuits, high-voltage signal processing circuits, and high-voltage interconnect structures, while the ASIC die handles only low-voltage operations. This segmentation isolates high-voltage operations from the ASIC die, eliminating dielectric breakdown and signal interference issues that would occur if high-voltage routings traversed both dies.
2Ease of manufacture
If high-voltage routings are contained within sensor die only, then manufacturing complexity is reduced, but electrical connection between dies must be established
Solution Approach 1:
The patent extracts high-voltage routing functions from the ASIC die and places them exclusively in the sensor die. This extraction simplifies the ASIC die design and manufacturing process, as it no longer needs to handle high-voltage signals. The sensor die independently manages all high-voltage operations, including generating high-voltage signals, processing them, and routing them to photodetector elements, thereby reducing overall manufacturing complexity despite the added inter-die connection requirement.
3Adaptability or versatility
If high-voltage and low-voltage operations are integrated on same die, then device integration is achieved, but handling both metal routings becomes complex and costly
Solution Approach 1:
The patent applies segmentation by dividing the system into two separate functional dies: the sensor die handles high-voltage operations and the ASIC die handles low-voltage operations. This segmentation allows each die to be optimized for its specific voltage domain, simplifying the manufacturing process for each. The sensor die can use simpler metal routing structures designed for high-voltage signals, while the ASIC die uses standard low-voltage routing, avoiding the complexity and cost of designing and manufacturing a single die that handles both high-voltage and low-voltage metal routings.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the development cycle time for BSI SPAD image sensors by avoiding high-voltage metal verification and demonstration, and lowers manufacturing costs by simplifying the handling of high-voltage and low-voltage metal routings.
Implementation Method 1
bonding a sensor die to an ASIC die with high-voltage interconnect structures contained within the sensor die
Data Source
AI summary
The present disclosure describes a semiconductor device that includes a first die bonded to a second die with interconnect structures in the first die. The first die includes a photodiode having first and second electrodes on a first side of a first dielectric layer, and first, second, and third interconnect structures in the first dielectric layer. The first and second interconnect structures are connected to the first and second electrodes, respectively. The second electrode has a polarity opposite to the first electrode. The second and third interconnect structures extend to a second side opposite to the first side of the first dielectric layer. The second die includes a second dielectric layer and a fourth interconnect structure in the second dielectric layer. The second dielectric layer is bonded to the second side of the first dielectric layer. The fourth interconnect structure connects the second and third interconnect structures.